Method and apparatus for constructing verification test sequence

Details Method and apparatus for constructing verification test sequence Method and apparatus for constructing verification test sequence

1995-03-06

1997-12-30

Beausoliel, Jr., Robert W.

Excavating

364578, G01R 3128, G06F 1100

Patent

active

057038856

ABSTRACT:
A Distinctness Measurement (DM) is determined (16) for Finite State Machine (FSM) state transitions. The DM is used to identify Unique Input/Output Sequence (UIO) Sets (63) that uniquely identify FSM (33) states. UIO Set members are combined with FSM transitions to form Test Subsequences (TS). Test Subsequences are connected (64) into Hierarchical TS Graphs (65), which are merged (38). The merged TS Graph (39) is augmented (94) and Euler Toured (28) to generate Verification Test Sequences (VTS). A VTS (43) tests conformance of a Machine-Under-Test (14) against a FSM (33) model.

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Kwang-Ting Cheng et al., Automatic Functional Test Generation Using the Finite State Machine Model 30th ACM/IEEE Design Automation Conference, p. 86, 1993.

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