Method and apparatus for constraining the compaction of componen

Details Method and apparatus for constraining the compaction of componen Method and apparatus for constraining the compaction of componen

1994-11-22

1997-06-03

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364490, G06F 1500

Patent

active

056361327

ABSTRACT:
Integrated circuit design method and apparatus with user defined constraints for constraining compaction of an integrated circuit layout. Logical boundary constraints allow a user to move layout designs to different process technologies without concern that device size changes will disrupt the layout. Multiple grid constraints allow a user to set grids of different sizes for the same or different circuit layers in a design. And pre-compaction constraints may be imposed by a user to preserve components' relationships in an initial topology throughout the compaction process.

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