Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-11-22
2004-10-12
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06804695
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method and apparatus for controlling Finite Impulse Response (FIR) filters typically used in hard disk storage systems for digital computers. In particular, present invention relates to method and apparatus for constraining the tap coefficients supplied to the FIR filter to minimize phase and gain discontinuity when switching between the acquisition and data reception periods.
2. Related Art
In the read channel of a hard disk drive, the read/write heed passes over the magnetic medium and outputs analog read pulses that alternate in polarity. These pulses are then decoded by read channel circuitry to reproduce the recorded digital data. Decoding the pulses into a digital sequence is typically performed by a discrete time sequence detector in a sampled amplitude read channel. There are several well-known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision feedback (FDTS/DF).
Sampled amplitude detection, such as partial response (PR) with Viterbi detection, allows for increased data density by compensating for intersymbol interference (ISI) and the effect of channel noise. Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate) Before sampling the pulses, a variable gain amplifier adjusts the read signal's amplitude to a nominal value, and a low pass analog filter filters the read signal to attenuate aliasing noise. After sampling, a digital equalizer filter equalizes the sample values according to a desired partial response, and a discrete time sequence detector, such an a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., maximum likelihood sequence detection (MLSD)). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to magnetic storage systems is well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, “A PRML System for Digital Magnetic Recording” IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, “Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel”, IEEE Trans. Commum., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, “Implementation of PRML in a Rigid Disk Drive”, IEEE Trans. On Magnetics, Vol. 27, No. 6, November 1991, and Carley et al, “Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection”, Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, “Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback”, IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, “Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel”, Globecom '90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; a Abbott et al, “Performance of Digital Magnetic Recording with Equalization and Offtrack Interference”, IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, “Adaptive Equalization in Magnetic-Disk Storage Channels”, IEEE Communication Magazine, February 1990, and Roger Wood, “Enhanced Decision Feedback Equalization”, Intermag '90, all of which are incorporated herein by reference.
Sampled amplitude detection requires timing recovery in order to correctly extract the digital sequence. Rather than process the continuous signal to align peaks to the center of bit cell periods as in peak detection systems, sampled amplitude systems synchronize the pulse samples to the baud rate. In conventional sampled amplitude read channels, timing recovery synchronizes a sampling clock by minimizing an error between the signal sample values and estimated sample values. A pulse detector or slicer determines the estimated sample values from the read signal samples. Even in the presence of ISI the sample values can be estimated and, together with the signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
A phase-locked-loop (PLL) normally implements the timing recovery decision-directed feedback system. The PLL comprises a phase detector for generating a phase error based on the difference between the estimated samples and the read signal samples. A PLL loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate. Typically, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
As mentioned above, sampled amplitude read channels also commonly employ a discrete time equalizer filer to equalize the sample values into a desired partial response (PR4, EPR4, EEPR4, etc.) before sequence detection. To this end, adaptive algorithms have been applied to compensate in real time for parameter variations in the recording system and across the disk radius. For example, U.S. Pat. No. 5,381,359 (incorporated herein by reference) discloses an adaptive equalizer filter that operates according to a well-known least mean square (LMS) algorithm. The LMS adaptive equalizer filter is a closed loop feedback system that attempts to minimize the mean squared error between an actual output of the filter and a desired output by continuously adjusting the filter's coefficients to achieve an optimum frequency response.
A problem associated with adaptive equalizer filters in sampled amplitude read channels is that the timing recovery and gain control loops can interfere with the adaptive feedback loop, thereby preventing the adaptive equalizer filter from converging to an optimal state. This non-convergence is manifested by the filter's phase and gain response drifting as it competes with the timing and gain control loops. An article by J. D. Coker et al. entitled “Implementation of PRML in Rigid Disk Drive”, published in IEEE Transactions on Magnetics, vol. 27, No. 6, November 1991, suggests a three tap transversal filter comprising a fixed center tap and symmetric side taps in order to constrain the phase response of the equalizer filter except in terms of a fixed group delay. Constraining the phase response of the adaptive equalizer in this manner, however, is a very sub-optimal method for attenuating interference from the timing recovery and gain control loops. Furthermore, it significantly reduces control over the adaptive filter's phase response, thereby placing the burden of phase compensation on the analog equalizer. Solutions to this problem have been proposed in U.S. Pat. Nos. 5,818,655 and 5,999,355, each of which is incorporated herein by reference. However, such solutions come at a high processing cost.
Another problem associated with adaptive equalizer filters is that the signal acquisition time is an overhead to the system throughput capacity. In order to reduce the acquisition time period, it is typical for the channel processor to switch from the FIR filter output to the filter input d
Mai Tan V.
Marvell International Ltd.
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