Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2003-02-27
2008-12-09
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S221000, C712S225000
Reexamination Certificate
active
07464251
ABSTRACT:
A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to the saturation signal. The carry chains support carry operations for non-local functions comprising minimum and maximum arithmetic functions.
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Broadcom Corporation
Pan Daniel
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