Method and apparatus for configuration and testing of large faul

Details Method and apparatus for configuration and testing of large faul Method and apparatus for configuration and testing of large faul

1990-12-07

1994-03-29

Beausoliel, Jr., Robert W.

Excavating

371 211, 371 216, G06F 1100

Patent

active

052992020

ABSTRACT:
In a large semiconductor memory having multiple memory modules that are addressable by a logical page address and a word address within each page, a technique for automatically testing the modules to establish a pool of good modules; then allocating each logical page of memory to a group of modules, with each module in the group being assigned to a particular bit position in all of the data words in the page. After allocation of each page, the modules in the page are tested in various ways to verify that they are fully functional. Modules not passing any of the tests are replaced by others from the pool of good modules. If the pool is exhausted, a partial page is de-allocated. Tests performed on the modules making up a logical page include a random access memory test, a test on bus connections to each module, and tests on the other major components of each module.

REFERENCES:
patent: 4066880 (1978-01-01), Salley
patent: 4191996 (1980-03-01), Chesley
patent: 4468731 (1984-08-01), Johnson et al.
patent: 4566102 (1986-01-01), Hefner
patent: 4653050 (1987-03-01), Vaillancourt

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