Method and apparatus for configurable build-in self-repairing of

Details Method and apparatus for configurable build-in self-repairing of Method and apparatus for configurable build-in self-repairing of

1994-12-28

1996-11-19

Canney, Vincent P.

Excavating

365201, G01R 3128

Patent

active

055770509

ABSTRACT:
A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.

REFERENCES:
patent: 4757503 (1988-07-01), Hayes et al.
patent: 5153880 (1992-10-01), Owen et al.
patent: 5377146 (1994-12-01), Reddy et al.

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