Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
1999-09-24
2002-10-29
Frejd, Russell (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S014000, C716S030000, C716S030000
Reexamination Certificate
active
06473726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of circuit design emulation. More particularly, this invention relates to the subject of emulation system utilization efficiency.
2. Background
With advances in integrated circuit technology, various tools have been developed to aid circuit designers in designing and debugging highly complex integrated circuits. In particular, emulation systems comprising reconfigurable emulation resources such as reconfigurable logic chips, reconfigurable interconnects, and so forth, have been developed for circuit designers to quickly “realize” their designs and emulate operation of the circuits.
Emulation systems known in the art all suffer from at least one common disadvantage in that they are merely equipped to allow one circuit design to be emulated at a time. Since not all circuit designs will require all emulation resources of an entire emulation system to emulate, prior art emulation systems are inefficient in facilitating utilization of the available emulation resources. The inefficiency has increased over the years as more and more emulation resources are packed into the newer emulation systems to accommodate emulation of the ever more complex integrated circuits being designed. Unfortunately, there is no abatement in sight to this undesirable inefficiency trend. Thus, a more efficient approach to utilizing emulation resources of an emulation system is desired.
SUMMARY OF THE INVENTION
An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the reconfigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.
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Frejd Russell
Schwabe Williamson & Wyatt P.C.
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