Boots – shoes – and leggings
Patent
1991-03-05
1992-05-12
Harkcom, Gary V.
Boots, shoes, and leggings
364759, G06F 738
Patent
active
051133636
ABSTRACT:
Method and apparatus for processing on-line operands A, B and C to produce the arithmetic expression S=(A.times.B)+C. In general, the apparatus includes an input processing unit, an on-line multiplication unit, and an on-line serial addition unit. The input processing unit is sequentially introducing the digits of operands, A, B and C into the apparatus, where each digit is represented in a redundant binary number format. The multiplication unit multiplies the sequence of digits of the operands A and B to produce the n-th product digit p.sub.n of the product P=A.times.B, with the most significant digit p.sub.o being computed first. The on-line addition unit adds the n-th product digit to the n-th digit of on-line operand C, so as to produce the n-th digit s.sub.n of the arithmetic expression S=(A.times.B)+C, with the most significant digit s.sub.o being produced first. In one embodiment, the input processing unit includes a selective conversion subunit for selectively converting the digits of operands A, B and C sequentially entering the computational device, so that each digit is represented in a redundant number format. In such an embodiment, the redundant binary number format is characterized by signed digit numbers, and the selective conversion subunit includes a binary-to-signed digit converter.
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Design and VLSI Implementation Of An On-Line Algorithm, by D. Ercegovac, et al., vol. 698 Real Time Signal Processing IX (1986), Society of Photo Optical Instrumentation Engineers (SPIE), p. 92.
A General Method For Evaluation Of Functions And Computations In A Digital Computer, by Milos Dragutin Ercegovac, Jul., 1975, Library of the University of Illinois, Microfilm No. 76-6758.
Orsino Francesco
Wang Chung-Tao D.
Ail Systems, Inc.
Harkcom Gary V.
Mai Tan V.
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