Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2005-02-22
2005-02-22
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S022000
Reexamination Certificate
active
06859870
ABSTRACT:
A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction sharing opportunities. Such opportunities are encoded in the control bits of the instruction. Before the instruction is moved into the instruction cache, the instruction is compressed into the new format to delete select redundant occurrences of a subinstruction. Specifically, where a subinstruction is to be shared by corresponding functional processing units of respective clusters, the subinstruction need only appear in the instruction once. The redundant appearance is deleted. The control bits are decoded at instruction parsing time to route a shared subinstruction to the associated functional processing units.
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Berg Stefan G.
Kim Donglok
Kim Yongmin
Sun Weiyun
Chan Eddie
Koda Steven P.
Li Aimee J.
University of Washington
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