Method and apparatus for compiling three-dimensional digital ima

Communications: electrical – Land vehicle alarms or indicators – Internal alarm or indicator responsive to a condition of the...

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

340703, 340750, 340747, 340717, G09G 128

Patent

active

044397607

ABSTRACT:
A method and apparatus, comprising a video data bus (8), a plurality of video memory modules (VM1-VMN), and bus arbitration circuits (BAC1-BACN) associated with each video memory module, are disclosed for compiling digital image information for display. A data processor (1) addresses the plurality of video memory modules over a processor data bus (2), the data processor for assigning a priority value to picture element data stored in the video memory modules. Upon command of the data processor, a frame (5 to 300) of picture element data is serially compiled on the video data bus (8). Data contention between video memory modules for access to the video data bus is controlled by the bus arbitration circuits, the picture element data bidding with the highest priority value gaining access. In one embodiment, the priority value represents the depth of a point of a solid object for display and/or the relative depth of picture element data comprising the object for display. The data processor may change the priority value associated with picture element data for display as well as the coordinates of data location in the display. Accordingly, textual characters having the highest priority and solid objects having a lesser priority may appear to move in front of one another on a background having the lowest priority value without interference in a sequence of frames of information for display.

REFERENCES:
patent: 3925776 (1975-12-01), Swallow
patent: 3944997 (1976-03-01), Swallow
patent: 4074233 (1978-02-01), Swain
patent: 4217577 (1980-08-01), Roe et al.
patent: 4222048 (1980-09-01), Johnson
patent: 4240140 (1980-12-01), Stafford et al.
patent: 4317114 (1982-02-01), Walker
patent: 4324401 (1982-04-01), Stubben et al.
Computer Design, "Semiconductor Advances Boost Digital Image Processing System Performance," Sep. 1979, pp. 93-101, by Harry C. Andrews.
Computer Design, "Bit Map Architecture Realizes Raster Display Potential," Jul. 1980, pp. 111-117, by Robert J. Gray.
IEEE Catalog No. EHO 156-0, "Interactive Computer Graphics," pp. 149-150, 201-202, and 331, by Herbert Freeman.
Electronics, "Video Display Processor Simulates Three Dimensions," Nov. 20, 1980, pp. 123-126, by Karl Guttag and John Hayn.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for compiling three-dimensional digital ima does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for compiling three-dimensional digital ima, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for compiling three-dimensional digital ima will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1758211

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.