Method and apparatus for compensating for timing variances...

Details Method and apparatus for compensating for timing variances... Method and apparatus for compensating for timing variances...

2006-08-22

2006-08-22

Tse, Young T. (Department: 2611)

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

C375S371000, C370S517000, C713S503000

Reexamination Certificate

active

07095817

ABSTRACT:
A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device that initially receives the N bit digital data signal, and a sink device that receives the N bit digital data signal from the source device. The N bit digital data signal has a skew when received by the sink device. A skew detection circuit in the sink device detects the skew in the N bit digital data signal and generates a skew detection signal. A line supplies the skew detection signal to the source device. A compensation circuit in the source device receives the skew detection signal and compensates for the skew in the N bit digital data signal.

REFERENCES:
patent: 5568526 (1996-10-01), Ferraiolo et al.
patent: 6232806 (2001-05-01), Woeste et al.
patent: 6516040 (2003-02-01), Lecourtier et al.

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