Electric power conversion systems – Current conversion – With means to introduce or eliminate frequency components
Reexamination Certificate
2001-10-02
2002-11-05
Vu, Bao Q. (Department: 2838)
Electric power conversion systems
Current conversion
With means to introduce or eliminate frequency components
C363S098000, C363S132000, C363S137000
Reexamination Certificate
active
06477067
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
The present invention relates to motor controllers and more particularly to a method and an apparatus for compensating for switching device drops and switching device dynamics in inverter systems.
One type of commonly designed motor is a three phase motor having three Y-connected stator windings. In this type of motor, each stator winding is connected to an AC voltage source by a separate supply line, the source providing time varying voltages across the stator windings. Often, an adjustable speed drive (ASD) will be positioned between the voltage source and the motor to control motor speed by controlling the stator voltages and frequency.
Many ASD configurations include a pulse width modulated (PWM) inverter consisting of a plurality of switching devices. Referring to
FIG. 1
, an exemplary PWM inverter leg
10
corresponding to one of three motor phases includes two series connected switches
12
,
13
between positive and negative DC rails
18
,
19
and two diodes
16
,
17
, a separate diode in inverse parallel relationship with each switch
12
,
13
. By turning the switches
12
,
13
ON and OFF in a repetitive sequence, leg
10
receives DC voltage via rails
18
and
19
and provides high frequency voltage pulses to a motor terminal
22
connected to a stator winding
24
. By firing the switching devices in a regulated sequence the PWM inverter can be used to control both the amplitude and frequency of voltage that is provided across winding
24
.
Referring to
FIG. 2
, an exemplary sequence of high frequency voltage pulses
26
that an inverter might provide to a motor terminal can be observed along with an exemplary low frequency alternating fundamental or terminal voltage
28
and related alternating current
30
. By varying the widths of the positive portions
32
of each high frequency pulse relative to the widths of the negative portions
34
over a series of high frequency voltage pulses
26
, a changing average voltage which alternates sinusoidally can be generated. The changing average voltage defines the terminal voltage
28
that drives the motor. The terminal voltage
28
in turn produces a low frequency alternating current
30
that lags the voltage by a phase angle &phgr;.
The hardware that provides the firing pulses to the PWM inverter includes both a control board and a power board. The control board includes, among other components, a processor that receives a frequency command signal and various feedback signals and, in response thereto, provides command signals to the power board. The power board converts the command signals to modulating signals. Among other things, the power board typically includes a comparator that receives each of at least one modulating signal and a carrier signal for comparison. Referring to FIG.
3
(
a
), exemplary modulating and carrier waveforms used by a power board to generate the firing pulses for leg
10
are illustrated. As well known in the art, a carrier waveform
36
is perfectly periodic and operates at what is known as a carrier frequency. A modulating voltage waveform
38
generally and ideally is sinusoidal, having a much greater period than carrier waveform
36
.
Referring also to FIGS.
3
(
b
) and
3
(
c
), an ideal upper signal
40
and an ideal lower signal
42
generated by a PWM comparator comparing the signals of FIG.
3
(
a
) and that may control the upper and lower switches
12
,
13
respectively, are illustrated. The turn-on times tu
1
, tu
2
and turn-off times to 1, to 2 of the upper and lower signals
40
,
42
, respectively, come from the intersections of the modulating waveform
38
and the carrier waveform
36
.
When the modulating waveform
38
intersects the carrier waveform
36
while the carrier waveform has a positive slope, the upper signal
40
goes OFF and lower signal
42
goes ON. On the other hand, when the modulating waveform
38
intersects the carrier waveform
36
while the carrier waveform has a negative slope, the upper signal
40
goes ON and the lower signal
42
goes OFF. Thus, by comparing the carrier waveform
36
to the modulating waveform
38
, the states of the upper and lower signals
40
,
42
, respectively, can be determined.
While the modulating and carrier signals are referred to as waveforms in order to simplify understanding of this explanation, in reality, each of the waveforms is a digital count that represents a corresponding waveform. For instance, the modulating waveform may be converted into a count that oscillates within a range between a first or minimum modulating count equal to or greater than zero and a second or maximum modulating count. Where the modulating waveform is sinusoidal, the modulating count changes in a sinusoidal time-varying fashion indicative of the waveform. In this case, a carrier count oscillates in a linear time varying fashion from zero to a maximum carrier count T
cmax
that is equal to or greater than the maximum modulating count and back to zero during each carrier cycle. The comparator compares the modulating count with the carrier count and when the modulating count is greater than the carrier count, causes the corresponding upper and lower switches to be turned ON and OFF, respectively, and when the modulating count is less than the carrier count, causes corresponding upper and lower switches to be turned OFF and ON, respectively. Because the modulating count value determines the ratio of switch ON times to PWM period duration (i.e., carrier cycle period), the modulating count is also referred to as a duty cycle Ts.
When the duty cycle count is less than one-half the maximum carrier count, the resulting terminal voltage is negative because the corresponding lower switch is ON for more than half the PWM period. Similarly, when the duty cycle count is greater than one-half the maximum carrier count, the resulting terminal voltage is positive because the corresponding upper switch is ON for more than half the PWM period.
Referring also to FIGS.
2
and
3
(
d
), an ideal high frequency voltage pulse
26
resulting from the ideal upper and lower signals
40
,
42
in FIGS.
3
(
b
) and
3
(
c
) that might be provided at terminal
22
can be observed. When the upper signal
40
is ON and the lower signal
42
is OFF, switch
12
allows current to flow from the high voltage rail
18
to motor terminal
22
thus producing the positive phase
44
of pulse
26
at motor terminal
22
. Ideally, when the upper signal
40
goes OFF and the lower signal
42
goes ON, switch
12
immediately turns OFF and switch
13
immediately turns ON connecting motor terminal
22
and the low voltage rail
19
producing the negative phase
46
of pulse
26
at terminal
22
. Thus, the ideal high frequency voltage pulse
26
is positive when the upper signal
40
is ON and is negative when the lower signal
42
is ON. Also, ideally, the low frequency terminal voltage and corresponding current (see
FIG. 2
) should completely mirror the modulating waveforms.
Unfortunately, these ideal switch operating conditions do not occur as there are several switch and inverter operating phenomenon that cause terminal voltage distortions. For example, one problem with PWM inverters has been that the high frequency terminal voltage pulses (see
26
in
FIG. 2
) cause ripple in the resulting low frequency phase voltages and currents. This ripple distortion has generally been addressed by either providing line filters that tend to smooth the ripple or by adopting faster switching technology. Elaborate filters are bulky and expensive and therefore are not preferred. Current inverter switching technology has advanced rapidly and modern switches are now capable of changing state in as little as several tens of nano-seconds (e.g., 50 nsec.). For this reason, recent inverter designs have typically adopted high speed switching configurations to reduce ripple distortion.
One other relatively well understood and th
Kerkman Russel J.
Leggate David
Gerasimow Alexander M.
Jaskolski Michael A.
Rockwell Automation Technologies Inc.
Vu Bao Q.
Walbrun William R.
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