Method and apparatus for compensating for bit line delays in sem

Details Method and apparatus for compensating for bit line delays in sem Method and apparatus for compensating for bit line delays in sem

1990-12-20

1993-09-14

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365210, G11C 700

Patent

active

052455840

ABSTRACT:
A method for compensating for bit line delays in semiconductor memories including the steps of developing a dummy word line signal representative of the delay of a word line of a semiconductor memory and controlling the sense amplifier of the semiconductor memory with a control signal derived, at least in part, from the dummy word line signal. Preferably, the dummy word line signal is delayed by a fixed delay or by delay produced by a proportionally loaded dummy bit line. A circuit embodying the method of the present invention includes a dummy word which produces a dummy word signal upon the activation of any word of the semiconductor memory and a delay coupling the dummy word signal to the clock input of the sense amplifier. The delay may be a fixed delay including a number of logic elements, or it may be developed by a proportionally loaded bit line which has a fraction of the load of an actual bit line of the semiconductor memory. In either embodiment, the sense amplifier is clocked soon after the bit lines of the semiconductor memory are ready for sensing.

REFERENCES:
patent: 4435793 (1984-03-01), Ochii
patent: 4520466 (1985-05-01), Mashiko
patent: 4985865 (1991-01-01), Houston
patent: 5031153 (1991-07-01), Suyama
patent: 5105385 (1992-04-01), Ohtsuka et al.
patent: 5124951 (1992-06-01), Slemmer et al.
patent: 5132931 (1992-07-01), Koker

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