Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Compensation for variations in external physical values
Reexamination Certificate
2002-07-26
2004-10-12
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Compensation for variations in external physical values
C327S513000, C330S289000
Reexamination Certificate
active
06803803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the electronic arts and more particularly to compensation circuits for counteracting the effects of variations in process, temperature and supply voltage, particularly in the context of delay circuits.
2. Description of Related Art
Delay circuits are known in the art. In many applications, it is useful to be able to apply a prescribed delay to a signal's propagation time (i.e. increase the propagation time) between two or more locations in an integrated circuit, or phase shift one signal relative to another signal. One such example is the need to compensate for delays in the distribution of clock signals and/or the delay in propagation of logic signals (see U.S. Pat. No. 6,127,865).
Another example of the use of delay circuits is to provide a prescribed delay to a data signal in order to compensate for a data signal path that is shorter than a clock signal path (see U.S. Pat. No. 6,163,195).
As signaling speed and integrated circuit density and complexity increase, there is an increasing need to provide more precisely prescribed delay times. One set of problems in implementing delay circuits that deliver precisely prescribed delay times have to do with the effect of variations in temperature, voltage supply, and process on the delay time provided by the delay element. These effects require further explanation. Each can affect current flow which in turn affects delay times. For example, as temperature increases, current flow decreases (as materials become more resistive) and delay time increases. This relationship between temperature and delay is illustrated in
FIG. 1
a.
Supply voltage levels also affect current and therefore delay time. As supply voltage increases, current flow also increases and delay time decreases. This relationship between supply voltage and delay is shown in
FIG. 1
b.
Effects due to supply voltage are sometimes referred to herein as simply “supply effects”, “effects due to supply,” or like phrases.
The variations in parameters of the fabrication and finishing process used to deliver an integrated circuit (IC) chip may also affect delay. These effects may cause actual delay to differ from the calculated or intended delay were the design specifications met perfectly. For example, across a wafer, inconsistencies in device elements may cause departures between actual and designed delay. Such inconsistencies could be from uneven polishing, temperature gradients, etc. resulting in device variations across a wafer. This may also relate to wafers being manufactured at different points in time, or at different locations within the processing machine. For example, a diffusion furnace may be set at 500.0 C one day, and the next 500.1 C the next. Each temperature will give slightly different device performances. Temperature differences may also exists simultaneously in different portions of the furnace. These various effects will sometimes be referred to herein as “process effects”, “effects due to process”, and like phrases.
FIG. 1
c
illustrates that different process parameters can result in different delays. For the sake of illustration, process effects that cause elements to run “slow” are shown to be associated with resulting high delay times and process effects that cause elements to run “fast” are shown to be associated with resulting low delay times.
Those skilled in the art will appreciate that
FIGS. 1
a,
1
b,
and
1
c
are very general illustrations meant only to show over all relationships between temperature/supply/process on the one hand, and delay on the other.
Some attempts have been made to correct for the effects that temperature, supply, and process have on signals. For example, in the context of generating and distributing clock signals, it is known to insert into the feedback of a PLL (phase lock loop) delay circuitry that maps the actual clock distribution network in order to generate a phase shifted clock signal that tracks the effects that variations in temperature, supply, and process have on the delay of a reference clock signal distributed through the clock signal network. (See U.S. Pat. No. 6,127,865, col. 1, lines 41-57).
However, a drawback of relying solely on PLL circuits to track temperature, supply, and process is that PLL circuits are complex and require many elements. Another approach is to use a delay chain with a bias circuit that provides a bias voltage to control current through the delay chain and to vary the bias voltage (and hence vary a bias current) to compensate for factors whose variation affects delay times. With respect to the effect of temperature, such an approach has been disclosed in U.S. Pat. No. 6,163,195. That patent teaches the use of a bias circuit that adjusts a bias voltage applied to a delay chain in response to changes in temperature thereby helping compensate for temperature effects on a delay provided by the delay chain.
However, a delay circuit is still needed that includes a compensating bias circuit that compensates for effects in addition to temperature. In particular, a delay circuit is needed that includes a bias circuit that compensates for the effects of variations in temperature, supply, and process.
SUMMARY OF THE INVENTION
The present invention provides a compensating bias circuit connected to drive a bias current that compensates for the effects that variations in temperature, supply, and process have on a delay time of a delay circuit. By providing compensation for factors that include temperature, process, and supply, the present invention addresses the need for a delay circuit having a compensating bias circuit for providing more consistent delays across a variety of conditions.
REFERENCES:
patent: 4477737 (1984-10-01), Ulmer et al.
patent: 5021684 (1991-06-01), Ahuja et al.
patent: 5578945 (1996-11-01), Flora
patent: 5994945 (1999-11-01), Wu et al.
patent: 6127865 (2000-10-01), Jefferson
patent: 6163195 (2000-12-01), Jefferson
patent: 2002/0057121 (2002-05-01), Lee
Lai Kang Wei
Starr Greg
Altera Corporation
Morrison & Foerster / LLP
Nguyen Minh
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