Pulse or digital communications – Spread spectrum
Reexamination Certificate
1999-09-01
2001-09-18
Vo, Don N. (Department: 2631)
Pulse or digital communications
Spread spectrum
C375S376000, C327S148000, C327S157000, C331S017000, C331S034000
Reexamination Certificate
active
06292507
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to image forming, computing, or microprocessor-based equipment and is particularly directed to spread spectrum clock generators of the type which reduce electromagnetic interference emissions. The invention is specifically disclosed as an automatically compensating spread spectrum clock generator that measures the pulse-width of the phase locked loop UP and DOWN signals and compares the actual pulse-width durations to typical or to predetermined values, and varies system parameters to correct any deviation error.
BACKGROUND OF THE INVENTION
Hi-speed digitally clocked systems are typically very noisy with regard to electromagnetic interference (EMI) emissions, unless some special care is taken at the design stage of equipment incorporating such clocked systems. One reliable and low-cost method for reducing EMI emissions is to use a spread spectrum clock such as is disclosed in U.S. Pat. Nos. 5,488,627 and 5,631,920. These patents disclose circuits in which the spread spectrum frequencies are varied by the use of programmable counters and by data stored in a memory circuit. These U.S. Pat. Nos. 5,488,627 and 5,631,920 are commonly-assigned, and are incorporated herein by reference in their entireties.
In a U.S. patent application, Ser. No. 09/169,110 (filed Oct. 8, 1998), a digital spread spectrum clock circuit is disclosed in which the clock is made variable by using Random Access Memory and a multiplexer to receive initiation data before the clock circuit is ready to run normally. This application is titled “Variable Spread Spectrum Clock,” and is commonly-assigned to Lexmark International, Inc., and is incorporated herein by reference in its entirety.
While such prior spread spectrum clocks have often been disclosed or constructed using phase locked loop circuits, other types of frequency synthesizer circuits can be made into a spread spectrum clock, including digital locked loop circuits and delay locked loop circuits. One example of a digital locked loop circuit is disclosed in U.S. Pat. No. 5,079,519, and one example of a delay locked loop circuit is disclosed in U.S. Pat. No. 5,771,264.
The spread spectrum clock generator (SSCG) designs previously available have a design sensitivity to the voltage controlled oscillator gain, charge pump current, and passive component values (in connection with phase locked loop circuits). It would be an improvement to correct, automatically or under control of a computer program, the sensitive parameters by modifying the SSCG circuit.
SUMMARY OF THE INVENTION
Accordingly, it is a primary advantage of the present invention to provide a spread spectrum clock generator that automatically compensates for variations in passive component values, voltage control oscillator gain, and charge pump current, to provide a more accurate and lower EMI emission clock circuit. It is another advantage of the present invention to provide a spread spectrum clock generator that automatically compensates for variations in VCO gain, charge pump current, and passive component values using either a microprocessor-based control system, or a purely hardware logic control system. It is a further advantage of the present invention to provide a spread spectrum clock generator that automatically compensates for variations in VCO gain, charge pump current, and passive component values, while using an accurate external clock to calibrate an error-detecting circuit which measures “peak” (or maximum) UP and DOWN signals of a Phase Locked Loop circuit, or other frequency synthesizer system. It is a yet further advantage of the present invention to provide a spread spectrum clock generator that can be set up in a production line environment and, once the set-up is completed, will operate at the customer's site to compensate for the initial values of VCO gain, charge pump current, and passive component values, in which these component values are sufficiently repeatable so as to not require further set-up or calibration procedures once on the site.
Additional advantages and other novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention.
To achieve the foregoing and other advantages, and in accordance with one aspect of the present invention, an improved spread spectrum clock generator circuit is provided which automatically compensates for variations in Voltage Controlled Oscillator gain and charge pump current in a Phase Locked Loop internal circuit, as well as for variations in passive component values. The present invention can be applied in a similar manner to other types of frequency synthesizer systems that have some similarities to Phase Locked Loop circuits, including those having signals that are analogous to Phase Locked Loop UP and DOWN signals. In a preferred embodiment, the UP and/or DOWN outputs of the Phase Frequency Detector (PFD) are monitored at certain times to determine the “peak” (or maximum) pulse-width of these UP and DOWN signals, and after an error (if any) is determined as compared to nominal (or typical) values for these pulse-width duration times in the UP and DOWN signals, the Phase Locked Loop (PLL) system is adjusted depending upon the magnitude and direction of the error signal. If the charge pump current magnitudes are approximately the same, then only one of the UP or DOWN signals need be measured.
Changes in the PLL gain parameters, especially the VCO gain and charge pump current, have a significant effect on the PFD outputs, such that the pulse-width of the UP and DOWN signals vary as the frequency changes along the spread spectrum profile. At one portion of the profile, the “peak” (i.e., maximum) pulse width of these UP and DOWN signals will be a function of the modulation profile and the PLL parameters. By measuring this peak pulse width of the UP and DOWN signals and comparing them to a theoretical pulse width, a compensation factor can be determined to offset this error. An automatic compensation scheme can be implemented by adjusting any one or combination of certain operating parameters of the circuit, including VCO gain, charge pump current, loop filter values, table values, and base number.
A Phase Locked Loop (PLL) circuit is the basis of the present invention, in which the output of the Voltage Controlled Oscillator (VCO) is directed into a divide-by-N circuit (also sometimes called a divide-by-N counter), and the output of this divide-by-N circuit is directed back to the Phase Frequency Detector (PFD) as the feedback signal. A reference signal, preferably a very accurate clock having a known frequency, is provided as the other input to the PFD circuit. This reference signal may itself be a divided signal, having a fraction of a system clock's output frequency.
As is well known in the art, the outputs of the PFD circuit are the UP and DOWN error signals, which are pulses that will be output quite often in a spread spectrum clock generator because the divide-by-N circuit will purposefully introduce an error at the feedback input of the PFD on a periodic basis. It is the accurate measuring of the pulse width of the UP and DOWN signals that makes the present invention feasible, because the theoretical pulse width is compared to the actual pulse width, and the compensation of any error is based upon this accurate measurement.
A preferred spread spectrum profile has rather distinct peaks and valleys, and will produce a corresponding error profile (i.e., the curve plotting the pulse widths of the UP and DOWN “error” signals) that also is somewhat “peaky.” These profiles are created and controlled by introducing a different value for N at the divide-by-N counter, which forces a new frequency or phase to be emitted by the VCO, which is caused by forcing the PFD circuit to output either UP or DOWN pulses to the charge pump. In the preferred profile, there are 128 different time intervals that succ
Hadady Craig Eric
Hardin Keith Bryan
Brady John A.
Lexmark International Inc.
Vo Don N.
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