Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Reexamination Certificate
1998-09-30
2001-05-15
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
C345S182000, C345S182000, C345S213000
Reexamination Certificate
active
06232952
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer graphics systems, and more specifically to a method and apparatus for generating a clock signal synchronized with a reference clock signal.
2. Related Art
There is often a need to generate a clock signal (“target clock signal”) which is synchronized with a reference clock signal. The two clock signals generally have unequal frequencies. For the purpose of illustration, the target clock signal may need to have a frequency of X/Y times the frequency of the reference clock signal, wherein X and Y are integers.
U.S. Pat. No. 5,739,867 entitled, “A Method and Apparatus for Upscaling an Image in Both Vertical and Horizontal Directions”, Issued Apr. 14, 1998, naming as inventor Alexander Julian Eglit, discloses an example situation in which such a need arises. The patent discloses a scaling circuit which scales a source image of A×B pixels into a destination image of C×D pixels without requiring large memories. The scaling circuit there scales the image by using a destination clock signal having ((C×D)/(A×B)) times the frequency of a source clock. The source clock is used as a reference clock and the destination clock is the target clock signal.
In a prior system, synchronization may be achieved by dividing a target clock signal by X and the source system clock by Y, comparing the phase of the resulting divided clock signals, and adjusting the phase of the target clock signal. Such a technique may be used in environments using digital or analog phase lock loops (PLLs) as is well known in the relevant arts.
In general, a target clock signal is more accurately synchronized with a reference clock signal if the time between successive comparisons (“comparison cycles”) is small because the shorter comparison cycles enable the phase of the target clock signal to be adjusted more frequently. Accordingly, both X and Y may be divided by a common denominator (CD), and the resulting numbers may be respectively used instead of X and Y. The comparison cycles may be shorter proportionate to the CD. in the upscaler embodiment noted above, the number of comparison cycles within a frame equals the CD used to divide (A×B ) and (C×D).
However, it may not be possible to make the comparison cycles short in several situations. For example, in the above technique, the greatest common denominator (GCD) of X and Y can be a number as low as 1. Such a situation may be further illustrated with the upscaler of U.S. Pat. No. 5,739,867. If a source image of size 800×600 pixels is to be upscaled to an image of size 1901×1501, only a very low GCD may be present. The upscaled image size may be specified by a user using a suitable user interface. A low GCD may lead to large comparison cycles.
Large comparison cycles may be problematic in several situations. For example, in techniques using PLLs to generate a target clock signal, large synchronization periods may result in large settling times and phase jitter. Phase jitter typically leads to display artifacts. Large settling times may be unacceptable as the tracking and correction abilities of the PLLs may be under-utilized. The problems caused by underutilization depend on the environment in which the PLL is used. For example, a monitor (e.g., using an upscaler according to U.S. Pat. No. 5,739,867) may take unacceptably long time in starting to display an image when a target image size is changed.
Furthermore, computation of CDs for large numbers and/or the division of X and Y by the CD may require unacceptably long time or complex circuits.
Accordingly, what is needed is an effective method and apparatus for synchronizing a target clock signal with a reference clock signal.
SUMMARY OF THE INVENTION
The present invention is directed to clock generation circuits which generate a target clock signal synchronized with a reference clock signal. Specifically, a phase comparator is provided, which compares frequently the phases of a target clock signal and a reference clock signal, and generates signals representative of the relative phase of the two signals. The generated signals can be used to adjust the phase of the target clock signal.
A phase comparator in accordance with the present invention may include a first circuit to generate a waveform representative of the incremental phase advancement of the reference clock signal, and a second circuit for generating a waveform representative of the incremental phase advancement of the target clock signal.
In an embodiment, the two waveforms are designed to have the same frequency such that the phase of the two waveforms represent the phase advancement of the two clock signals. To simplify the comparison process, the two waveforms may be generated such that the instantaneous amplitude is reflective of the phase of the waveform.
Thus, a sample may be taken at the same time point (synchronously) of the two waveforms, and the samples are compared to determine the phase relationship of the reference and target signals. The phase of the target clock signal is adjusted to according to the result of the comparison.
The manner in which the two waveforms (having same frequency and with the amplitude reflecting the phase advancement) can be generated is illustrated with reference to generating a target clock signal which may need to have a frequency of (X/Y) times the frequency of the reference clock signal. Two phase accumulators are maintained, with the output of each phase accumulator representing the incremental phase advancement of the corresponding clock signal.
The first phase accumulator is incremented by X for each clock tick (or clock period) of the reference clock signal, and the second accumulator is incremented by Y for each clock tick of the target clock signal. As may be readily appreciated, the outputs of the phase accumulators represent the incremental phase advancement of the corresponding clock signals, and samples (at the same time point) on the waveforms can be taken for adjusting the phase of the target signal.
A micro view of such waveforms readily reveals that the two waveforms are advanced as steps, with amplitude difference between steps of X for the first waveform (corresponding to the reference clock signal), and a difference of Y for the second waveform. The time duration of each step in the steady-state is inversely proportional to the amplitude difference, with the result that the two waveforms have the same phase advancement over a reasonably long duration.
Therefore, a graph of the instantaneous amplitude difference of the two waveforms would reveal small differences even if the target and reference clock signals are perfectly synchronized. The differences would average out to zero over some duration. A signal representing these small differences may be termed as ripple.
As the differences represented by the ripple would average out to zero, it is generally desirable that the phase of the target signal not be modified due to such differences. Therefore, an aspect of the present invention provides a circuit to minimize or eliminate the tracking of the ripple components. For example, a combination of approaches (noted below) can be used for such a purpose.
The comparison cycle may be made reasonably long by effecting phase correction only once a few potential sample points on the waveforms. In addition, only phase differences greater than a predetermined magnitude may be used in modifying the phase of the target clock signal.
Furthermore, a multiplexor may be employed which selects the output of the phase comparator of the present invention only when the target clock signal phase may need to be modified quickly, while selecting the output of other circuits during steady state. As a result, the present invention may quickly synchronize the target signal with a reference clock signal, while eliminating the ripple effects during steady state.
A low pass circuit can also be used at the output of the phase comparator such that short term changes do not affect the pha
Dinh Duc Q
Genesis Microchip Corp.
Hjerpe Richard
Law Firm of Naren Thappeta
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