Method and apparatus for clock uncertainty minimization

Details Method and apparatus for clock uncertainty minimization Method and apparatus for clock uncertainty minimization

1999-11-12

2000-12-05

Zweizig, Jeffrey

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

327292, H01L 2500

Patent

active

061572519

ABSTRACT:
A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

REFERENCES:
patent: 5557235 (1996-09-01), Koike
patent: 5717359 (1998-02-01), Matsui et al.

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