Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1993-04-30
1994-05-03
Sikes, William L.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307511, 307603, 328 63, H03L 700, H03K 513
Patent
active
053090357
ABSTRACT:
An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.
REFERENCES:
patent: 3820030 (1974-06-01), Williams
patent: 4443766 (1984-04-01), Belton, Jr.
patent: 4475085 (1984-10-01), Yahata et al.
patent: 4604582 (1986-08-01), Strenkowski
patent: 4675612 (1987-06-01), Adams et al.
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 4755704 (1988-07-01), Flora et al.
patent: 4998025 (1991-03-01), Watanabe
patent: 4999526 (1991-03-01), Dudley
patent: 5087829 (1992-02-01), Ishibashi et al.
"VLSI Performance Compensation for Off-Chip Drivers and Clock Generation" by Dennis T. Cox et al. from Proceedings of IEEE 1989 Custom Integrated Circuits Conference, pp. 14.3.1-14.3.4.
"Dynamically Tracking Clock Distribution Chip With Skew Control" by Dave Chengson et al. From Proceedings of IEEE 1990 Custom Integrated Circuits Conference, pp. 15.6.1-15.6.4.
"A Variable Delay Line Phase Locked Loop For CPU-Coprocessor Synchronization" by Mark G. Johnson et al. from Proceedings of IEEE 1988 International Solid-State Circuits Conference, at pp. 142-143.
Collins Hansel A.
Iknaian Russell
Watson, Jr. Richard B.
Cefalo Albert P.
Cunningham Terry D.
Digital Equipment Corporation
Maloney Denis G.
Sikes William L.
LandOfFree
Method and apparatus for clock skew reduction through absolute d does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for clock skew reduction through absolute d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for clock skew reduction through absolute d will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2116804