Method and apparatus for clock skew reduction through absolute d

Details Method and apparatus for clock skew reduction through absolute d Method and apparatus for clock skew reduction through absolute d

1991-09-23

1993-12-21

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307511, 307603, 328 63, H03K 513, H03L 700

Patent

active

052723909

ABSTRACT:
An "absolute" delay regulator of a clock repeater chip performs a precise measurement of the propagation delay of a clock signal and adjusts that delay so as to maintain a fixed-phase relationship with an input clock signal. A replica loop accurately replicates the internal path and external loading, including input and output buffers, of the chip. The output of the replica loop drives a delay line whose tapped outputs provide an absolute delay measurement. Results of the measurement are decoded and used to select an appropriate tap to another delay line used to insert a desired amount of delay to an output clock signal.

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