Method and apparatus for clock recovery in a digital display uni

Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source

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348537, 348512, 345501, G09G 512

Patent

active

057963924

ABSTRACT:
A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

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