Method and apparatus for clock and data recovery with high jitte

Details Method and apparatus for clock and data recovery with high jitte Method and apparatus for clock and data recovery with high jitte

1989-05-16

1991-10-08

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

375120, 341 69, 331 17, H04L 7033

Patent

active

050561189

ABSTRACT:
Apparatus and method are disclosed for implementing a clock and data recovery circuit for use on digital networks. A fully integrated phase-locked loop extracts a clock signal embedded in a data stream. Two trimming digital-to-analog converters simultaneously bring the center frequency of a current controlled oscillator and the phase-locked loop closed loop bandwidth to desired values. A triple sampler captures jittering data and aligns them with the recovered clock. The input jitter tolerance for the method and apparatus is two to three times that of previously reported phase-locked loop based circuits.

REFERENCES:
patent: 3657653 (1972-04-01), Wilkinson
patent: 4617679 (1986-10-01), Brooks
patent: 4773085 (1988-09-01), Cordell
patent: 4803705 (1989-02-01), Gillingham et al.
Charge-Pump Phase-Lock Loops, Floyd M. Gardner IEEE Transactions on Communications, vol. COM-28, No. 11, Nov. 1980, pp. 1849-1858.
Phase-Frequency Detector MC4344.multidot.MC4044, MTTL Complex Functions, Motorola Semiconductor Products, Inc., Printed Nov. 1983.

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