Method and apparatus for clock and data delivery on a bus

Details Method and apparatus for clock and data delivery on a bus Method and apparatus for clock and data delivery on a bus

1991-11-22

1994-08-30

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

H04L 2300

Patent

active

053435036

ABSTRACT:
A bus termination scheme that minimizes signal reflection and that minimizes the effect of the number of devices coupled to the bus. In this invention, a resistor is provided between a signal driver and the transmission bus. In addition, a resistance is provided between the bus and each receiving means. The driver resistor reduces the effective capacitance of the transmission line as well as effectively source terminating the line. The receiver resistor reduces effective capacitance and damps signal reflections. Thus, the performance of the bus is increased by minimizing the effects of the number of drivers and receivers on the bus. In addition, the drivers can be lower powered than prior art drivers because no static and a reduced dynamic load is presented to the driver. Finally, the resistors do not dissipate power continuously but only when a transmitter changes the bus state or potential, further enhancing low power operation. The present invention also provides a method for providing a clock signal from any signal source coupled to the bus. In a data transfer transaction, the present invention utilizes a protocol that permits the transfer of two data words with only a single acknowledgement so that the data rate is decoupled from the control signal rate. This permits data to be transmitted at a double word rate even though control signals are provided at a lower rate.

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