Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2006-01-31
2006-01-31
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C438S131000, C438S132000
Reexamination Certificate
active
06991970
ABSTRACT:
A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit. Various inventive embodiments and implementations are described.
REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5241496 (1993-08-01), Lowrey et al.
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5331196 (1994-07-01), Lowrey et al.
patent: 5345110 (1994-09-01), Renfro et al.
patent: 5838625 (1998-11-01), Cutter et al.
patent: 5898217 (1999-04-01), Johnston
patent: 5973978 (1999-10-01), Cutter et al.
patent: 6078100 (2000-06-01), Duesman et al.
patent: 6087707 (2000-07-01), Lee et al.
patent: 6088282 (2000-07-01), Loughmiller et al.
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6094388 (2000-07-01), Cowles
patent: 6097098 (2000-08-01), Ball
patent: 6108260 (2000-08-01), Casper
patent: 6154851 (2000-11-01), Sher et al.
patent: 6169329 (2001-01-01), Farnworth et al.
patent: 6169331 (2001-01-01), Manning et al.
patent: 6271574 (2001-08-01), Delpech et al.
patent: 6320242 (2001-11-01), Takasu et al.
patent: 6423582 (2002-07-01), Fischer et al.
patent: 6555458 (2003-04-01), Yu
patent: 6607945 (2003-08-01), Tsui
patent: 6753210 (2004-06-01), Jeng et al.
patent: 6774456 (2004-08-01), Rusch et al.
patent: 6809398 (2004-10-01), Wang
patent: 2002/0017729 (2002-02-01), Macpherson
patent: 2002/0020058 (2002-02-01), Saito et al.
patent: 2004/0012071 (2004-01-01), Ido et al.
patent: 2004/0209404 (2004-10-01), Wang et al.
patent: 6-232537 (1994-08-01), None
Synchronous DRAM 64Mb: x4, x8, x16 SDRAM, Micron Technology, Inc., p. 65-Rev D; Pub. May 2001.
Synchronous DRAM 64Mb: x32 SDRAM, Micron Technology, Inc., p. 65-Rev. Sep. 2000.
Synchronous DRAM 128Mb: x4, x8, x16 SDRAM, Micron Technology, Inc., p. 65-Rev. E; Pub. May 2001.
Cowles Timothy
Fogal Rich
Reynolds Tracy
Coleman W. David
Martin Kevin D.
Micro)n Technology, Inc.
Nguyen Khiem D.
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