Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With microwave gas energizing means
Reexamination Certificate
1999-11-02
2002-03-26
Mills, Gregory (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
With microwave gas energizing means
C451S066000, C451S278000
Reexamination Certificate
active
06361647
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of electronic devices. More particularly, the invention provides a technique including a method and device for planarizing a film of material of an article such as a semiconductor wafer. However, it will be recognized that the invention has a wider range of applicability; it can also be applied to flat panel displays, hard disks, raw wafers, and other objects that require a high degree of planarity.
The fabrication of integrated circuit devices often begins by producing semiconductor wafers cut from an ingot of single crystal silicon which is formed by pulling a seed from a silicon melt rotating in a crucible. The ingot is then sliced into individual wafers using a diamond cutting blade. Following the cutting operation, at least one surface (process surface) of the wafer is polished to a relatively flat, scratch-free surface. The polished surface area of the wafer is first subdivided into a plurality of die locations at which integrated circuits (IC) are subsequently formed. A series of wafer masking and processing steps are used to fabricate each IC. Thereafter, the individual dice are cut or scribed from the wafer and individually packaged and tested to complete the device manufacture process.
During IC manufacturing, the various masking and processing steps typically result in the formation of topographical irregularities on the wafer surface. For example, topographical surface irregularities are created after metallization, which includes a sequence of blanketing the wafer surface with a conductive metal layer and then etching away unwanted portions of the blanket metal layer to form a metallization interconnect pattern on each IC. This problem is exacerbated by the use of multilevel interconnects.
A common surface irregularity in a semiconductor wafer is known as a step. A step is the resulting height differential between the metal interconnect and the wafer surface where the metal has been removed. A typical VLSI chip on which a first metallization layer has been defined may contain several million steps, and the whole wafer may contain several hundred ICs.
Consequently, maintaining wafer surface planarity during fabrication is important. Photolithographic processes are typically pushed close to the limit of resolution in order to create maximum circuit density. Typical device geometries call for line widths on the order of 0.5 &mgr;M. Since these geometries are photolithographically produced, it is important that the wafer surface be highly planar in order to accurately focus the illumination radiation at a single plane of focus to achieve precise imaging over the entire surface of the wafer. A wafer surface that is not sufficiently planar, will result in structures that are poorly defined, with the circuits either being nonfunctional or, at best, exhibiting less than optimum performance. To alleviate these problems, the wafer is “planarized” at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions, the required degree of planarization increases. As circuit dimensions are reduced, interconnect levels must be globally planarized to produce a reliable, high density device. Planarization can be implemented in either the conductor or the dielectric layers.
In order to achieve the degree of planarity required to produce high density integrated circuits, chemical-mechanical planarization processes (“CMP”) are being employed with increasing frequency. A conventional rotational CMP apparatus includes a wafer carrier for holding a semiconductor wafer. A soft, resilient pad is typically placed between the wafer carrier and the wafer, and the wafer is generally held against the resilient pad by a partial vacuum. Alternatively, the wafer is pushed against the pad in a configuration which applies a back-pressure to the wafer. This arrangement provides a certain degree of compliance for the wafer during polishing. The wafer carrier is designed to be continuously rotated by a drive means. In addition, the wafer carrier typically is also designed for transverse movement. The rotational and transverse movement is intended to reduce variability in material removal rates over the surface of the wafer. The apparatus further includes a rotating platen on which is mounted a polishing pad. The platen is relatively large in comparison to the wafer, so that during the CMP process, the wafer may be moved across the surface of the polishing pad by the wafer carrier. A polishing slurry containing chemically-reactive solution, in which are suspended abrasive particles, is deposited through a supply tube onto the surface of the polishing pad.
CMP is advantageous because it can be performed in one step, in contrast to prior planarization techniques which tend to be more complex, involving multiple steps. For example, planarization of CVD interlevel dielectric films can be achieved by a sacrificial layer etchback technique. This involves coating the CVD dielectric with a film which is then rapidly etched back (sacrificed) to expose the topmost portions of the underlying dielectric. The etch chemistry is then changed to provide removal of the sacrificial layer and dielectric at the same rate. This continues until all of the sacrificial layer has been etched away, resulting in a planarized dielectric layer.
Chemical-mechanical polishing is a well developed planarization technique. The underlying chemistry and physics of the method is understood. Certain limitations, however, exist with CMP. Specifically, CMP often involves a large polishing pad, which uses a large quantity of slurry material. The large polishing pad is often difficult to control and requires expensive and difficult to control slurries. Additionally, the large polishing pad is often difficult to remove and replace. The large pad is also expensive and consumes a large foot print in the fabrication facility. These and other limitations still exist with CMP and the like.
A recent advance is the use of a face-up polishing scheme in which the wafer is arranged in a face-up position. A pad having a smaller diameter than that of the wafer is brought down upon the surface to perform the polishing action. With this technique, however, it is very difficult to obtain smooth results near the center of the wafer. The result is a planarized wafer whose center region may or may not be suitable for subsequent processing. Sometimes, therefore, it is not possible to fully utilize the entire surface of the wafer. This reduces yield and subsequently increases the per-chip manufacturing cost with the consumer ultimately bearing the cost.
It is therefore desirable to maximize the useful surface of a semiconductor wafer to increase chip yield. What is needed is an improvement of the CMP technique to improve the degree of global uniformity that can be achieved using CMP.
SUMMARY OF THE INVENTION
A polishing apparatus according to the invention includes a chuck assembly for supporting a wafer to be polished. A pad assembly having a translation stage positions a polishing pad relative to a wafer to be polished. A controller provides control signals to operate the chuck and pad assemblies during a polish operation. The controller includes a data store for storing an offset distance and a velocity profile. The controller further includes control outputs to position the pad according to the stored offset distance and to translate the pad according to the stored velocity profile during polishing.
In accordance with the invention, the pad offset distance is determined by selecting a first offset distance. The pad is positioned relative to a test wafer based on this first offset distance. A polish of the test wafer is performed. The pad is translated at a constant velocity across the wafer. A removal profile of the resulting polished test wafer is then produced. Based on the characteristics of the removal profile, a second offset dista
MacArthur Sylvia R.
Mills Gregory
Stras Baugh
Townsend and Townsend / and Crew LLP
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