Excavating
Patent
1988-11-30
1991-04-09
Fleming, Michael R.
Excavating
371 101, 371 215, G06F 1110
Patent
active
050070533
ABSTRACT:
A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.
REFERENCES:
patent: 4368532 (1983-01-01), Imazeki
patent: 4698808 (1987-10-01), Ishii
patent: 4726024 (1988-02-01), Guziak
patent: 4727544 (1988-02-01), Brunner
patent: 4782486 (1988-11-01), Lipcon
patent: 4807186 (1989-02-01), Ohnishi
David A. Patterson, Garth Gibson, Randy H. Katz, "A Case For Redundant Arrays of Inexpensive Disks (RAID)", published in ACM SIGMOD Conference, Chicago, Ill., (May 1988).
Dias Daniel M.
Dishon Yitzhak
Iyer Balakrishna R.
Drumheller Ronald L.
Fleming Michael R.
Ilardi Terry J.
International Business Machines - Corporation
LandOfFree
Method and apparatus for checksum address generation in a fail-s does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for checksum address generation in a fail-s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for checksum address generation in a fail-s will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2040421