Method and apparatus for checking the parity of disassociated bi

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364738, G06F 1110

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044621027

ABSTRACT:
A method and apparatus for determining the parity of data bits that have been disassociated from their parity bits and regrouped by a data byte shifter/converter or like apparatus. The lack of usually available parity bit association is overcome by generating a parity bit for each of the groups, including the parity bits, formed by the disassociative procedure. The group parity bits are then logically checked by an appropriate number of exclusive OR gates to determine their overall parity. A resultant parity signal is thereby generated which accurately reflects the parity state of the original data, unless an even number of bit errors have occurred. An odd number of bit errors is detected and, if appropriate, then alarmed.

REFERENCES:
patent: 4155070 (1979-05-01), Munter
patent: 4224681 (1980-09-01), Lewine
patent: 4251884 (1981-02-01), Baun, Jr.
Low, "Shared Parity Checker", IBM Tech. Disclosure Bulletin, vol. 11, No. 7, Dec. 1968, pp. 882-883.
Macak et al., "Parity Check Circuit for Unequal Byte Size Transfers", IBM Tech. Disclosure Bulletin, vol. 11, No. 10, Mar. 1969, p. 1248.
Grimes, "Address Error Checker for Remote & Local Scattered Bits", IBM Tech. Disclosure Bulletin, vol. 22, No. 2, Jul. 1979, pp. 456-457.

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