Method and apparatus for checking the address and contents of a

Details Method and apparatus for checking the address and contents of a Method and apparatus for checking the address and contents of a

1991-06-24

1994-06-14

Canney, Vincent P.

Excavating

371 215, 371 491, G06F 1100

Patent

active

053217063

ABSTRACT:
A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

REFERENCES:
patent: 4692893 (1987-09-01), Casper
patent: 4785452 (1988-11-01), Petz et al.
patent: 5142541 (1992-08-01), Kim et al.

Affiliated with

Also associated with

Rating

Method and apparatus for checking the address and contents of a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for checking the address and contents of a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for checking the address and contents of a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1254923