Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-02-10
2002-08-06
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06429677
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the field of reliability testing of integrated circuits. More particularly, the invention relates to an apparatus and method for reliability stressing of thin gate and node dielectrics for low voltage technologies.
Semiconductor manufacturers who make integrated circuit chips begin by manufacturing semiconductor wafers. Each wafer is typically 100 mm, 125 mm, 150 mm, 200 mm or 300 mm in diameter and contains anywhere from one to several thousand chips or die on the wafer. When manufacture of the wafer is completed, chips or die are cut or “diced” from the wafer and may later be mounted into single chip or multiple chip packages for implementation in a printed circuit board or other applications.
When manufacture of a wafer is completed, it is customary practice to test each chip on the wafer to determine whether each chip, as manufactured, electrically matches design criteria, matches performance criteria of the system in which the chip is to be implemented, and will be reliable in operation.
Logic circuit manufacturers routinely perform both logic and parametric tests on their products. To test the “logic” of a circuit, a typical tester stimulates various terminals of the circuit with input logic signals while monitoring various output logic signals produced by the tester in response to the input logic signal stimulus to determine if the output signals exhibit expected logic patterns. A “parametric” test measures analog characteristics of the circuit at its terminals. One of the most important parametric characteristics of a logic circuit is its leakage current, the amount of current an input terminal of a logic circuit sources or sinks when the terminal is driven to a high or low logic level. Leakage current is typically measured by connecting the terminal to a voltage source through a precision resistor and measuring the voltage drop across the resistor. Multiple devices are tested in parallel. The voltage drop is proportional to the leakage current. The possibility of excessive leakage creates difficulty in selecting an appropriate resistor value. A small value resistor potentially allows excessive current drain under device short circuit conditions and causes too small of a voltage drop for precise characterization for normal leakage readings. Conversely, a large resistor value will cause in a large voltage drop resulting in excessive impact on the stress voltages being applied to the device under test (DUT).
Reliability “logic” testing is used to screen out chips having an undesirably short life span. Typically, a significant percentage of a group of chips will fail early in their lifetime due to marginal conditions during manufacture. Subsequently, a very low percentage of the group will fail during an extended period of use of the chips. Reliability screening of semiconductor chips is typically performed by a process of supplying test signal patterns to chips under test to repeatedly stimulate all devices and wires on a chip, and is typically performed at elevated temperatures and/or voltages to simulate the first six months of operation. Therefore, the screening procedure is known as burn-in.
Reliability engineering “parametric” testing of integrated circuits is used to predict product lifetimes and calculate defect densities over the life of the component. In particular, the characterization of gate dielectric leakage currents provides reliability engineers with information critical to life cycle predictions. This process of characterization has historically been time consuming and expensive for semiconductor manufacturers. To accomplish this in a short time, it is necessary to subject product samples to environmental conditions that accelerate the failure modes that cause wearout.
Typical methods for creating these stress conditions include the use of temperature and voltage such that the temperature stress used for testing exceeds the operating temperature stress when the circuit is in actual use, and such that the stress voltage used for testing exceeds the operating voltage when the circuit is in actual use.
Voltage acceleration has been used as the primary factor for gate and node dielectric stressing throughout CMOS history. Mathematical models were then applied in order to project a characterization of the dielectric from stressed testing conditions. Typically, gate dielectrics are subjected to stress voltage levels for a period of time. The voltage is then lowered to the normal operating levels and the leakage current measured. This is referred to as stress induced leakage current (SILC) testing. SILC testing is often performed at additional voltages close to nominal operating levels for more robust characterizations.
Many manufacturers have attempted to address low throughput of burn-in and characterization processes by creating burn-in boards onto which many diced chips are placed in chip packages, and then the packages go into sockets on the burn-in boards. Thereafter, each chip on the test board is simultaneously exercised. Thus, many chips are burned-in at once. These systems effectively reduce the time required to burn-in a large volume of chips.
However, the increased number of diced chips also increases the physical complexity of taking data. In the case of gate dielectric leakage current characterization, each device requires a read back of voltage and current which is two pairs of wires for every device on the board. These wires multiply quickly to create fragile connections and unwieldy boards.
For the forgoing reasons, there is a need for an apparatus and simple method of measuring the leakage current of a large number of gate dielectrics over an extended period of time in a fully automated way. Additionally, there is a need for lowering acceleration of life stress voltages thereby giving longer test times without sacrificing throughput.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for reliability characterization of integrated circuit dice gate dielectrics by monitoring of leakage current. Pursuant to the present invention, provision is made for the continual monitoring of the gate dielectric leakage current on each of a plurality of devices.
The teachings of the invention are in three principal areas. The first is an apparatus for monitoring and recording multiple gate dielectric leakage currents during a reliability characterization test. The large number of devices tested allows for longer testing at lower voltages thereby minimizing the need to rely on mathematical models to project dielectric characteristics. The apparatus employs on board solid-state multiplexers (MUX) at multiple levels of test apparatus assembly to eliminate excess wiring and allow for constant scan monitoring of the DUTs without concern for wearout of electro-mechanical switches. The MUXs and DUTs are mounted on circuit cards wherein connections are made by circuit runs on the cards. With appropriate addressing, the MUXs allow for a single output to accommodate all DUT measurements thus eliminating wires from each DUT.
The present invention provides a second inventive approach for selectively recording the data resultant from the constant scanning of the leakage currents. In accordance with this aspect of the invention, fewer data readings per fixed time period are stored during quiescent periods and multiple readings are stored when the leakage current is changing more rapidly. Thus the resolution of the data is maximized during the critical phase of dielectric breakdown allowing for more precise characterizations of gate dielectrics without the need to increase data storage.
The third inventive facet of the invention is an efficient and expeditious methodology for assuring the accuracy of the readings when switching between voltage stress levels. Constant voltage levels are supplied to the DUTs by circuitry employing operational amplifiers (op-amps) commonly known to those of ordinary skill in the art. The output of an op-amp is affected by inherent characteristics that
Anderson Jay
Cantor & Colburn LLP
Kobert Russell M.
Sherry Michael
LandOfFree
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