Wave transmission lines and networks – Frequency multipliers
Reexamination Certificate
1999-09-03
2002-05-14
Pascal, Robert (Department: 2817)
Wave transmission lines and networks
Frequency multipliers
C333S032000, C327S119000, C327S122000, C327S123000, C455S314000, C455S333000
Reexamination Certificate
active
06388546
ABSTRACT:
FIELD OF INVENTION
This invention relates to a method and an apparatus for multiplying the output frequency of an oscillator, and is particularly concerned with cascading frequency doublers to provide frequency sources in the microwave and millimeter-wave frequency bands.
BACKGROUND OF THE INVENTION
Emerging high-data-rate wireless communication systems in the Ka band, require highly-stabilized, low phase-noise signal sources, and the phase-locked oscillator (PLO) is considered a promising candidate. The construction of millimeter-wave PLOs, however, necessitates a complex circuitry consisting of several radio frequency (RF) components, often resulting in a cumbersome packaging and high total cost along with high DC power consumption. Recently, millimeter-wave injection-locked oscillators have been investigated to exploit low-GHz synthesizer sources comprised with low-cost ICs, as reported in:
Kamogawa et al., “Injection-locked oscillator chain: a possible solution to millimeter-wave MMIC synthesizers,” 1996 IEEE MTT-S Symposium Digest, pp. 517-520; and Suematsu et aL, “Millimeter-wave HBT MMICs synthesizers using sub-harmonically injection-locked oscillators,” 1997 IEEE GaAs IC Symposium Digest, pp. 271-274. These methods, using high multiplication factors, are also an attractive means of
attaining better performance because the phase noise deterioration for frequency multiplication varies according to f
2
, while the phase noise of microwave and millimeter-wave oscillators reportedly degrades according to f
4
-f
5
, as indicated in:
Isots et aL, “Overview of millimeter-wave monolithic circuits,” 27th European Microwave Conference Proceedings, pp. 1316-1322 (Sept. 1997).
As an alternative to millimeter-wave PLOs, frequency multipliers have been conventionally employed following microwave PLOs. In order to achieve higher orders of multiplication, frequency multipliers are often constructed with chains of frequency doublers because frequency doubling has been preferred for its higher conversion efficiency. In such multipliers, diodes have been conventionally used as devices for frequency conversion, and is required the insertion of driving power amplifiers between doublers to compensate for the conversion losses accompanied by frequency multiplication.
Although possible conversion gain is expected by using transistors such as field-effect transistors (FETs), interstate amplifiers have been needed in high frequency ranges such as millimeter-wave frequencies where small-power devices have been used as reported in:
H. Wang, et aL, “A W-band source module using MMICs,” IEEEE Trans. Microwave Theory Tech., Vol MTT-43, No. 5, pp. 1010-1016, May 1995.
Depending on the capabilities of the devices and the operating frequency, frequency doublers have been cascaded without driving amplifiers as reported in:
Ninomiya et aL, “60-GHz transceiver for high-speed wireless LAN system,” 1996 IEEE MTT-S Symposium Digest, pp. 1171-1174; and
Hamada et al, “60GHz phase locked oscillator using frequency doubler”, 1997
IEICE Spring Conference C-2-45. However, in these systems, each stage has been an independent circuit whose input/output impedances are matched to 50 ohms at the respective frequencies.
A configuration of cascaded frequency doublers in accordance with the prior art is illustrated in
FIG. 1. A
first-stage frequency doubler
1
contains in a series connection a first input matching network
1
a
to provide 50 ohm matching for the fundamental frequency signal, a first transistor
1
b
, a first quarter-wavelength open-ended stub
1
c
for suppressing the fundamental frequency, followed by a first output matching network
1
d
to provide 50 ohm matching for the second harmonic frequency signal. A second-stage frequency doubler
2
contains in a series connection a second input matching network
2
a
to provide 50 ohm matching for the second harmonic frequency signal, a second transistor
2
b
, a second quarter-wavelength open-ended stub for
2
c
for suppressing the second harmonic frequency, followed by a second output matching network
2
d
to provide 50 ohm matching for the fourth harmonic frequency signal. U.S. Pat. No. 4,754,229 issued to Kawakami and Kudo on Jun. 28, 1988 describes a microwave design of a matching circuit having similar components to those shown in FIG.
1
.
The configuration shown in
FIG. 1
consists of cascaded frequency doublers where each stage is designed independently so that input/output impedances at each stage is matched to provide 50 ohm termination for its corresponding frequency. As a consequence, different stubs are required for matching 50 ohm in each input/output impedance matching network. Since relatively small-power devices are used, the power level is at most approximately 0 dBm. Employing medium-power transistors for increasing the driving power level results in the frequency bandwidth becoming narrower. This is because the input resistance of medium-power transistors, which is originally relatively low, is often even further lowered by a quarter-wavelength open-ended stub for suppressing the fundamental frequency, necessitating a larger transforming ratio to 50 ohm. For instance, a GaAs-based 500 &mgr;m PHEMT from Northrop Grumman Corporation shows the input resistance of approximately 5 ohm, hence the transforming ratio to 50 ohm is about 10. This ratio can become equivalently even higher by the effect of the quarter-wavelength open-ended stub. In the case of such large ratios, an additional impedance matching network may need to be employed if the circuit is to be terminated to 50 ohms with a sensible frequency bandwidth.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and an apparatus for multiplying the output frequency of an oscillator in low-frequency microwave bands.
It is another object of the invention to provide a highly stable, low-phase-noise local frequency source in microwave and millimeter-wave frequency bands.
Therefore, in accordance with an aspect of the present invention, there is provided a method of frequency multiplication comprising the steps of:
(a) receiving an input signal having a fundamental frequency component f
0
;
(b) providing an input impedance matching to said fundamental frequency component;
(c) performing a plurality of n frequency doubling operations in series to derive from the input signal an output signal having an output frequency component of 2
n
f
0
, wherein each frequency doubling operation, hereby referred to as k' th doubling operation K≦n, includes the steps of
receiving a k′ th input signal having an input frequency component of 2
(k-1)
f
0
,
deriving from the k′ th input signal a k′ th intermediate signal having a harmonic frequency component of 2
k
f
0
,
suppressing the input frequency component of 2
(k-1)
f
0
from the intermediate signal; and
(d) providing an interstage impedance matching to the harmonic frequency component of 2
k
f
0
between each pair of consecutive k' th and (k+1)′th frequency doubling operations; and
(e) providing an output impedance matching to the output frequency component of 2
n
f
0
. Preferably, each doubling operation step further includes a step of signal stabilization after the step of receiving said input signal.
In accordance with another aspect of the present invention there is provided a multistage frequency multiplier comprising in a series configuration:
(a) an input network for receiving an input signal having a fundamental frequency component of f
0
and for providing impedance matching to said fundamental frequency component;
(b) a plurality of n frequency doublers, to derive from the input signal an output signal having an output frequency component of 2
n
f
0
,
wherein each frequency doubler, hereby referred to as a k′ th doubler k<n, comprises
means for receiving a k′ th input signal having an input frequency component of 2
(k-1)
f
0
, and deriving from said input signal a k′ th intermediate signal having a harmonic frequency component of 2
k
f
0
, and
m
Kikokawa Masahiro
Stubbs Malcolm G.
Her Majesty The Queen In Right of Canada as represented by The M
Pascal Robert
Polster Lieder Woodruff & Lucchesi
Summons Barbara
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