Amplifiers – Involving structure other than that of transformers per se
Reexamination Certificate
1999-12-09
2001-10-09
Pascal, Robert (Department: 2817)
Amplifiers
Involving structure other than that of transformers per se
C330S292000, C330S302000, C330S310000
Reexamination Certificate
active
06300827
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to amplifiers. More particularly, the invention relates to grounding a cascaded series of amplifiers in an integrated circuit.
BACKGROUND OF THE INVENTION
In the transmission of electromagnetic radiation over antennae, amplification is usually necessary to achieve sufficient power to transmit signals by radiating an electromagnetic field. Similarly to receive signals, low level electromagnetic fields need to be amplified to sufficient power levels for circuitry to discern the received signal. The electromagnetic fields may be radiated at various frequencies but typically are associated with radio or microwave frequency ranges. In any case, it is desirable to provide efficient amplification of signals. Efficient amplification is proportional to the gain provided by an amplifier. Thus, it is desirable to increase both the gain and efficiency in the design of amplifiers used to amplify signals.
Prior art high frequency amplifiers typically use discrete components such as discrete capacitors, discrete inductors and discrete transistors because of they are easy to change out or modify if improperly designed or manufactured and are they are relatively inexpensive. Referring now to
FIG. 1A
, a discrete transistor
100
A is illustrated. Discrete transistor
100
A is in a packaged form and includes a single transistor circuit on a semiconductor die
102
. The base collector and emitter of the discrete transistor
100
A are output respectively on the base pin
104
, the collector pin
105
, and the emitter pin
106
. The base pin
104
is coupled to the base of the discrete transistor
100
A through the base bond wire
107
and the base bonding pad
110
. The collector pin
105
couples to the collector of the discrete transistor
100
A through the collector bonding wire
108
and the collector bonding pad
111
. The emitter pin
106
couples to the emitter of the discrete transistor
100
A through the emitter bonding wire
109
and the emitter bonding pad
112
. Referring now to
FIG. 1B
, a schematic diagram symbol of the idealized discrete transistor
100
B is illustrated. Discrete transistor
100
B includes the base pin
104
, the collector pin
105
and the emitter pin
106
. Referring now to
FIG. 1C
, a schematic diagram of the discrete transistor
100
C including parasitic elements is illustrated. In
FIG. 1C
, discrete transistor Q is illustrated including the parasitic elements associated with the discrete transistor
100
A. Discrete transistor
100
A has inherent parasitics due to the metal wire routing from each transistor terminal to the bonding pads which are represented by the base inductance L
b
, the collector inductance L
c
, and the emitter inductance L
e
. Inherent in the manufacturing of a transistor are capacitances between terminals. Between the base and collector is a base-collector capacitance C
bc
. Between the base and emitter there is a base-emitter capacitance C
be
. Between the collector and emitter is a collector emitter-capacitance C
ce
. These transistor parasitics are associated with semiconductor physics and the design and manufacture of the transistor in the semiconductor die
102
. Parasitic inductances are also associated with the bonding wires
107
-
109
connected between the bonding pads and the pins
104
-
106
and the pins themselves. These parasitic inductances from the bonding wires and pins are represented in
FIG. 1C
as the base bond wire inductance L
bwb
, the collector bond wire inductance L
bwc
, and the emitter bond wire inductance L
bwe
. In the preferred embodiment, transistor Q of discrete transistor
102
is designed and manufactured for the amplification of radio frequency signals. Alternatively, transistor Q may be designed and manufactured to operate within other ranges of transmission carrier frequencies.
Referring now to
FIG. 2A
, a block diagram symbol of a single-stage amplifier
200
is illustrated. Amplifier
200
is provided with a power supply input through amplifier ground AG. Signals input on the amplifier input A
IN
are amplified by a gain to generate the amplifier output A
out
. Referring now to
FIG. 2B
, a typical schematic diagram of the single-stage amplifier
200
is illustrated. The single stage amplifier
200
is illustrated with the idealized discrete transistor
100
of FIG.
1
B. The amplifier input A
IN
is coupled into the base of the discrete transistor
100
through the blocking capacitor C
block
. Amplifier ground AG is directly coupled preferably to the emitter
106
of the discrete transistor
100
. However, amplifier ground AG is not directly coupled into the emitter of transistor Q because of the parasitic inductance associated with the emitter and the package connections including a bond wire and the connecting pin itself. The amplifier output A
out
is provided at the collector
105
of the discrete transistor
100
.
Often times a single amplifier stage is insufficient to provide a sufficient amount of amplification. In order to provide greater amplification, two or more single amplifier stages may be coupled in series together to form a cascaded amplifier. Referring now to
FIG. 3A
, a block diagram of a cascaded amplifier
300
A is illustrated, having N single amplifier stages. Cascaded amplifier input Cin is input into the cascaded amplifier
300
A to generate the cascaded amplifier output Cout. The single amplifier stage, having the discrete transistor
100
illustrated in
FIG. 2B
is exemplary of each of the instances of amplifiers A
1
through A
n
. Typically the cascaded amplifier
300
A is implemented in a printed circuit board. Each of the amplifier stages are coupled in series together through the use of metallic printed circuit board traces. Except for the last stage, the output from one stage is coupled to the input of the next respective stage. The printed circuit board typically has a power supply provide the board power BP and board ground BG through their respective metal traces. Each of the discrete amplifiers are typically separately coupled to the board power BP and the board ground BG. The separate power coupling through the metal traces forms parasitic inductive components. Between amplifier power AP and board power BP there is a power trace inductance L
PT1
through L
PTn
. Similarly, parasitic inductance is formed through the metal trace between the amplifier ground AG and the board ground BG as represented by the ground trace inductances L
gt1
through L
gtn
.Each of the amplifier stages has an input inductance associated with the input wire trace of the printed circuit board. These are represented by the input trace inductances L
IT1
through L
Itn
. A trace output inductance L
outT
is also associated with the final output from the amplifier stage A
n
. Because the ground traces are typically connected to the same board ground BG, AC ground loop currents are formed in the inductances L
GT1
through L
GTn
when the amplifier is operating to amplify AC signals. In
FIG. 3A
, the AC ground loop currents i
1
through i
3
are illustrated. Because of the AC ground loop currents, the actual ground voltage provided to the amplifiers A
1
through A
n
, is actually elevated above zero volts when amplification occurs. This causes a degradation in the amplification provided by each of the amplifiers A
1
through A
n
when the ground coupled at each respective emitter rises.
Alternatively components of a cascaded amplifier may be implemented within an integrated circuit device. Referring now to
FIG. 3B
, a packaged integrated circuit
300
B for a four stage integrated circuit cascade amplifier
300
C is illustrated. The packaged integrated circuit
300
B has pins
304
,
305
-
305
D,
306
-
306
D which connect using bondwires to the die of the four stage integrated circuit cascaded amplifier
300
C. Referring now to
FIG. 3C
, the integrated circuit
300
C includes transistors Q
1
, Q
2
, Q
3
, and Q
4
and blocking capactors C
B1
, C
B2
, C
B3
, and C
B4
. The other elements illustrated in the schematic of
FIG. 3C
are
Blakely , Sokoloff, Taylor & Zafman LLP
Maxim Integrated Products Inc.
Nguyen Patricia
Pascal Robert
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