Data processing: measuring – calibrating – or testing – Calibration or correction system – Circuit tuning
Reexamination Certificate
2002-08-02
2004-07-20
Wachsman, Hal D (Department: 2857)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Circuit tuning
C702S191000, C716S030000
Reexamination Certificate
active
06766264
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the process of simulating digital circuits. More specifically, the present invention relates to a method and an apparatus for calibrating parameters of a model to be used in a simulation of a digital circuit.
2. Related Art
As integrated circuits continue to increase in density and operating speed, they are becoming more sensitive to noise caused by inductive and capacitive coupling between signal lines. This noise can interfere with the operation of an integrated circuit and hence must be considered during the process of routing of signal lines within the digital circuit.
Circuit designers typically use a computer-based model of a digital circuit to determine the effects of various circuit parameters, including inductive and capacitive noise, on performance of the digital circuit. The results of these circuit simulations can be used to verify that the digital circuit meets performance targets, and to iteratively adjust the design of the digital circuit.
Unfortunately, there presently exists no accurate way to determine the magnitude of the noise coupling parameters to be used in such a computer-based model. This leads circuit designers to make rough estimates of such noise coupling parameters or to ignore such parameters in developing a model. Hence, when the results determined from the model do not match the results measured from the physical circuit, there is no clear way to determine how to adjust the parameters to more accurately model the digital circuit.
What is needed is a method and an apparatus for accurately calibrating parameters to be used in a simulation of a digital circuit.
SUMMARY
One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.
In a variation on this embodiment, measuring how noise affects the amplitude of the signal on the victim net involves using multiple level detectors to quantize the signal on the victim net. The system then digitizes the output of these level detectors.
In a further variation, a given level detector includes a complementary metal oxide semiconductor inverter circuit.
In a further variation, the detection level of a given level detector is established by adjusting the beta of the complementary metal oxide semiconductor inverter circuit.
In a further variation, the system adjusts the beta by adjusting the ratio of &ohgr;
p
to &ohgr;
n
.
In a further variation, each level detector has a different beta.
In a further variation, a given level detector is followed by a series of inverters, which amplify and shape an output pulse.
In a further variation, digitizing the output of a given level detector involves latching the state of the last inverter of the series of inverters so that the state can be read to determine the output of the given level detector.
REFERENCES:
patent: 6029117 (2000-02-01), Devgan
patent: 6499131 (2002-12-01), Savithri et al.
patent: 6523149 (2003-02-01), Mehrotra et al.
patent: 6536022 (2003-03-01), Aingaran et al.
Ding et al., “Crosstalk noise estimation using effective coupling capacitance”, IEEE, International Symposium on Circuits and Systems, May 26-29, 2002, vol. 5, pp. V-645-V-648.*
Chen et al., “Aggressor alignment for worst-case crosstalk noise”, IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 2001, vol. 20, issue 5, pp. 612-621.
Jung Dae Suk
Lee Kyung
Grundler Edward J.
Park Vaughan & Fleming LLP
Wachsman Hal D
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