Method and apparatus for calibrating linear delay lines

Details Method and apparatus for calibrating linear delay lines Method and apparatus for calibrating linear delay lines

1989-09-21

1991-05-07

Cangialosi, Salvatore

Boots, shoes, and leggings

341120, G01R 3500

Patent

active

050142283

ABSTRACT:
A circuit for calibrating linear delay lines wherein a periodic ramp voltage is counted a fixed number of times at first and second frequencies. While the ramp voltages are being counted at each frequency, system clock pulses are counted. The number of system clock pulses counted for each first and second ramp voltage frequency is used to adjust the charging current applied to an integrator which establishes the delay value.

REFERENCES:
patent: 3685048 (1972-08-01), Pincus
patent: 3750142 (1973-07-01), Barnes et al.
patent: 4118698 (1978-10-01), Becker
patent: 4222107 (1980-09-01), Mrozowski et al.
patent: 4613950 (1986-09-01), Knierim et al.
patent: 4827437 (1989-05-01), Blanton et al.
patent: 4851838 (1989-07-01), Shier

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