Coded data generation or conversion – Converter calibration or testing
Patent
1997-06-30
1999-01-19
Williams, Howard L.
Coded data generation or conversion
Converter calibration or testing
H03M 110
Patent
active
058618260
ABSTRACT:
The calibration method preferably comprises the steps of: driving the analog-to-digital converter (ADC) with at least one test signal; calibrating the driven ADC over a series of successive ADC calibrations; generating a series of successive ADC figure of merit measurements for respective successive ADC calibrations, the series of successive ADC figure of merit measurements defining at least a portion of a curve having a local minimum/maximum; and stopping calibrating at an ADC calibration corresponding to the local minimum/maximum of the curve defined by the series of successive ADC figure of merit measurements. The step of calibrating preferably comprises incrementally calibrating the ADC over the series of successive ADC calibrations. The method preferably further comprises the step of determining the local minimum/maximum of the curve. In particular, the step of determining preferably comprises fitting an equation to the series of ADC figure of merit measurements; and calculating the local minimum/maximum based upon the equation. Of course, the step of fitting the equation preferably comprises fitting the equation based upon a predetermined number of prior ADC figure of merit measurements. The step of fitting the equation may comprise fitting a polynomial equation, such as a third order equation, to the series of ADC figure of merit measurements. In addition, the step of calculating the local minimum/maximum may preferably comprise calculating a first derivative of the equation.
REFERENCES:
patent: 4354177 (1982-10-01), Sloane
patent: 4903024 (1990-02-01), Evans et al.
patent: 5047772 (1991-09-01), Ribner
patent: 5057839 (1991-10-01), Koch
patent: 5140325 (1992-08-01), Yu et al.
patent: 5144311 (1992-09-01), Buhler et al.
patent: 5177484 (1993-01-01), Bruckmann
patent: 5196851 (1993-03-01), Patel et al.
patent: 5251162 (1993-10-01), Gazsi
patent: 5266951 (1993-11-01), Knegler et al.
patent: 5465092 (1995-11-01), Mayes et al.
patent: 5594439 (1997-01-01), Swanson
patent: 5594612 (1997-01-01), Henrion
patent: 5659312 (1997-08-01), Sunter et al.
Yuh-Min, et al., "A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-.mu.m CMOS", IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.
Douglas A. Mercer, "A 14-b 2.5 MSPS Pipelined ADC with On-Chip EPROM", IEEE Journal on Solid-State Circuits, vol. 31, No. 1, Jan. 1996.
Stephen H. Lewis, et al., "A 10-b 20-Msample/s Analog-to-Digital Converter", IEEE Journal on Solid-State Circuits, vol. 27, No. 3, Mar. 1992.
Tzi-Hsiung Shu, "A BiCMOS Fully-Differential 10-Bit 40MHz Pipelined ADC", IEEE Journal on Solid-State Circuits, pp. 154-157.
Shu Tzi-Hsiung
Von Dolteren George E.
Harris Corporation
Williams Howard L.
LandOfFree
Method and apparatus for calibrating integrated circuit analog-t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for calibrating integrated circuit analog-t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for calibrating integrated circuit analog-t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1250059