Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2001-03-30
2004-03-30
Deb, Anjan K. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S452000, C703S014000, C716S030000
Reexamination Certificate
active
06714027
ABSTRACT:
The present invention relates to a method of calculating the electrical characteristics of materials of thin film transistors (TFTs).
Having regard to the complexity and cost of the fabrication processes for manufacturing thin film transistors, it is highly desirable if not essential for the design and performance evaluation of such transistors to be undertaken using mathmatical simulations, often referred to as modelling. Crucial to such modelling is the acurate calculation of the electrical characteristics of materials of thin film transistors. Consequently, considerable effort has previously been spent in developing methods of calculating such characteristics. Such methods are usually embodied in computer programs which are often sold as staple commercial products by or on behalf their developers to designers and manufacturers of thin film transistors and other semiconductor products including such transistors.
Known methods of calculating the electrical characteristics of materials of thin film transistors suffer various disadvantages, common amongst which are relatively slow execution speeds (often of the order of one to two weeks) and often significant deviations of the calculated results from the real characteristics. Some known methods require the destructive testing of the sample. It is an object of the present invention to mitigate these and other disadvantages.
Thin film transistors are most often fabricated from polysilicon and this, as with alternative materials, consists of crystalline regions (grains), typically between a hundred to a few thousand angstroms in size, separated by grain boundaries. A high density of dangling bonds are present at these grain boundaries. These dangling bonds give rise to states all over the energy gap, due to their variable electronic energy levels. In addition, other gap states can be introduced as a Consequence of random fluctuations of the crystalline potential. These disorder-induced localised states are located in energy near the conduction and valence bands, and constitute the so-called tail states. In polysilicon, these states are probably associated with non-uniform strain fields, and may be distributed over the grain volume. As the density-of-states (DOS) is spatially non-uniform, the physical modelling of polysilicon is complex.
FIG. 1
shows two typical transfer curves of an n-channel polysilicon TFT, the typical structure of which is shown in FIG.
2
. The first case is when the drain to source voltage V
DS
is low (0.1v), and the second case when V
DS
is high (5,1v). For both cases, when the gate voltage V
GS
is small but positive, the current I
DS
which flows between the source and drain, due to V
DS
, is very small. This is due to the high resistance of the undoped active layer. As V
GS
is increased, charge is induced near the oxide-semiconductor interface and a conductive path known as the channel is formed between the source and the drain, hence resulting in an increase of I
DS
by several orders of magnitude. However, the electrical characteristics of these devices have a much lower apparent mobility and a higher apparent threshold voltage than their single crystal counterparts. This is due to the presence of a continuum of states in the energy gap (the DOS).
Several computer programs using a reverse modelling technique have been commercially available for a number of years. Various design and research groups have used these programs while adopting a distributed defect approximation. The approximation enables spatially localised DOS of polysilicon TFTs to be described assuming an effective DOS uniform over the grain volume. This is also known as the effective medium approach, whereby the effective DOS is considered to be uniformly distributed throughout the polyisilicon active layer thickness. These known methods are time consuming, taking anything from several hours to several weeks of computing time, and suffer uncertainties due to unknown parameters such as the flat band voltage and the Fermi energy.
The so-called field-effect method has become quite popular due to it's apparent simplicity. It suffers the disadvantages of the effective medium approach and can present serious shortcomings such as assuming a semi-infinite active layer thickness and no interface states. It suffers from various sources of inaccuracy. In particular, the flat band voltage (V
FB
), the bulk Fermi energy (E
F
) and the electron and hole contributions (G
n0
, G
p0
) to the conductance (G
O
) at the flat band voltage are not known. This may result in incorrect location of the DOS function along the energy axis. The 0° Kelvin approximation for the Fermi function must be assumed, which results in an overestimation of the DOS. Further, the use of the second derivative of the square of the surface field (F
S
) magnifies noise resulting in inaccuracies especially near mid gap, where oscillations larger than one order of magnitude are observed.
Another known method, the Temperature Method, relies upon the input data being functions of temperature. This method enables estimates to be made of the flat band voltage, the Fermi energy, the electron conductance (G
n0
) and the hole conductance (G
p0
). However, both the initial data capture and the analysis procedure are relatively complex. In particular, to obtain the input data requires the sample to be mounted in a cryostat. Uncertainties exist due to the temperature dependence of the Fermi function and the 0° Kelvin approximation and second derivative of the square of the surface field (F
S
) still exist.
With the increasing use of thinner active layers (<100 nm) the effect of the interface states is becoming more significant. Thus, it has been proposed to attempt to determine both the interface and bulk DOS; but such proposals have not dealt with the problems of determining the flat band voltage and the Fermi energy, neither have they avoided the uncertainties of the 0° Kelvin approximation and second derivative of the square of the surface field (F
S
).
Against this background the present invention provides, in a first aspect, an automated method a method of determining the bulk states and interface states of a polysilicon thin film transistor from a current-voltage measurement and a capacitance-voltage measurement, the current-voltage measurement being source/drain current (I
DS
) measurements relative to gate/source voltage (V
GS
): comprising the steps of:
a determining the minima of the capacitance-voltage measurement and assigning this value as the flat band voltage (V
FB
)
b using the flat band voltage (V
FB
) and the capacitance-voltage measurement to calculate the relationship between the gate surface potential (&psgr;
s
) and gate/source voltage (V
GS
), using the relationship that the charge on the gate (Q
G
) is equal to the integral of the product of the oxide capacitance per unit area (C
ox
) and the voltage drop across the oxide (V
ox
) and the relationship that the derivative of the gate surface potential (&psgr;
s
) with respect to the gate/source voltage (V
GS
) is a function of the gate width (W), channel length (L), the capacitance (C) measured between the gate and the drain/source contacts electrically connected together;
c using the calculated relationship between the gate surface potential (&psgr;
s
) and gate/source voltage (V
GS
), the relationship that the charge on the gate (Q
G
) is equal to the integral of the product of the oxide capacitance per unit area (C
ox
) and the voltage drop across the oxide (V
ox
), the relationship that the charge on the gate (Q
G
) is the sum of the surface charge (Q
ss
) and the bulk charge (Q
B
) where the the bulk charge (Q
B
) is the product of the dielectric permittivity of silicon (&egr;
S
) and the surface field (F
S
), which is the derivative of the calculated profile of the surface potential (&psgr;
x
); to calculate and output the interface states information;
d dividing the source/drain current (I
DS
) with the drain/source voltage (V
DS
) to obtain conductance/gate voltage data (G-V
GS
);
e using the conductance/
Lui Basil
Migliorato Piero
LandOfFree
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