Method and apparatus for calculating reciprocals and reciprocal

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

708605, G06F 7552

Patent

active

061157333

ABSTRACT:
A processor capable of efficiently evaluating constant powers of an operand such as the reciprocal and reciprocal square root is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to evaluate constant powers of an operand such as the reciprocal and reciprocal square root. Intermediate products that are formed may be rounded and normalized in two paths, one assuming an overflow will occur, and then compressed and stored for use in the next iteration. The processor comprises a multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier may performing rounded by adding a rounding constant.

REFERENCES:
patent: 3633018 (1972-01-01), Ling
patent: 3777132 (1973-12-01), Bennett, Jr.
patent: 4163287 (1979-07-01), Munter et al.
patent: 4573136 (1986-02-01), Rossiter
patent: 4607343 (1986-08-01), Chevillat et al.
patent: 4849923 (1989-07-01), Samudrala et al.
patent: 5157624 (1992-10-01), Hesson
patent: 5206823 (1993-04-01), Hesson
patent: 5343416 (1994-08-01), Eisig et al.
patent: 5606677 (1997-02-01), Balmer et al.
patent: 5633818 (1997-05-01), Taniguchi
patent: 5729481 (1998-03-01), Schwarz
patent: 5737255 (1998-04-01), Schwarz
patent: 5737257 (1998-04-01), Chen et al.
patent: 5841684 (1998-11-01), Dockser
A.D. Booth, "A signed binary multiplication technique," Quaterly Journal of Mechanics and Applied Mathematics, vol. 4, No. 2, pp. 236-240, 1951.
W.S. Briggs and D.W. Matula, "A 17x69 Bit multiply and add unit with redundant binary feedback and single cycle latency," in Proceedings of the 11.sup.th IEEE Symposium on Computer Arithmetic, Jul. 1993, pp. 163-170.
D.L. Fowler and J.E. Smith, "An accurate high speed implementation of division by reciprocal approximation," in Proceedings of the 9.sup.th IEEE Symposium on Computer Arithmetic, Sep. 1989, pp. 60-67.
J.A. Kowaleski, et al, "A dual execution pipelined floating-point CMOS processor," in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 1996, pp. 358-359.
N.T. Quach, et al, "On fast IEEE rounding," Technical Report No. CSL-TR-91-459, Computer Systems Laboratory, Standford University, Jan. 1991.
M.R. Santoro, et al, "Rounding algorithms for IEEE multipliers," in Proceedings of the 9.sup.th IEEE Symposium on Computer Arithmetic, Sep. 1989, pp. 176-183.
H.P. Sit, et al, "An 80 MFLOPS floating-point engine in the Intel i860 processor," in Digest of Technical Papers, IEEE International Conference on Computer Design, 1989, pp. 374-379.
Hennessy & Patterson, "Computer Architecture: A Quantitative Approach," Appendix A (pp. A-2 to A-53), Morgan Kaufmann Publishers, Inc., 1990.
Yu & Zyner, "167 MHz Radix-4 Floating Point Multiplier," SPACR Technology Business, Sun Microsystems, Inc., Sunnyvale, California, pp. 149-154.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for calculating reciprocals and reciprocal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for calculating reciprocals and reciprocal , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for calculating reciprocals and reciprocal will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2223006

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.