Method and apparatus for calculating delay for logic circuit and

Details Method and apparatus for calculating delay for logic circuit and Method and apparatus for calculating delay for logic circuit and

1997-08-25

2000-05-23

Teska, Kevin J.

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

703 14, 703 18, 716 6, G06F 1750

Patent

active

060661771

ABSTRACT:
In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.

REFERENCES:
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5452225 (1995-09-01), Hammer
patent: 5600273 (1997-02-01), Hall et al.
patent: 5703798 (1997-12-01), Dhar

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