Method and apparatus for calculating a divider in a digital phas

Details Method and apparatus for calculating a divider in a digital phas Method and apparatus for calculating a divider in a digital phas

1995-03-06

1996-01-23

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 1A, 331 11, 331 16, 331 17, 331DIG2, 327105, 327156, 375376, 455260, H03L 708, H03L 718

Patent

active

054867924

ABSTRACT:
A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital oscillator (23), and a loop filter (24). The first comparator (12), loop filter (24), digital oscillator (23), and feedback divider (20) of the DPLL (10) operate to produce a controlled oscillation. The second comparator (14), third comparator (16), and adjuster (18) provide a divisor to the feedback divider (20) that allows the DPLL (10) to operate with a variety of unknown system clock (22) frequencies.

REFERENCES:
patent: 4827225 (1989-05-01), Lee
patent: 5371480 (1994-12-01), Hedberg et al.
patent: 5424687 (1995-06-01), Fukuda

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