Boots – shoes – and leggings
Patent
1994-05-27
1995-08-15
Ramirez, Ellis B.
Boots, shoes, and leggings
395460, 395500, 395416, G06F 1208
Patent
active
054425719
ABSTRACT:
A computer system using virtual memory addressing and having a direct-mapped cache is operated in a manner to simulate the effect of a set associative cache by detecting cache misses and remapping pages in the main memory so that memory references which would have caused thrashing can instead coexist in the cache. Two memory addresses which are in different pages but which map to the same location in the cache may not reside in the direct-mapped cache at the same time, so alternate reference to these addresses by a task executing on the CPU would cause thrashing. However, if the location of one of these addresses in main memory is changed, the data items having these addresses can coexist in the cache, and performance will be markedly improved because thrashing will no longer result. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain the same virtual address. This is accomplished by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one. The thrashing condition is detected and corrected dynamically by latching cache miss addresses and periodically sampling the latch, then remapping pages containing the addresses found upon sampling. The direct-mapped cache must be large enough to hold two or more pages.
REFERENCES:
patent: 5101485 (1992-03-01), Perazzoli, Jr.
patent: 5119290 (1992-06-01), Loo et al.
patent: 5175834 (1992-12-01), Sawai
patent: 5210843 (1993-05-01), Ayers
Patterson et al, "Computer Architective-A Quantitative Approach", Morgan Kaufmann Publishers, Inc., 1990, pp. 419-424, 441-444, 454-474.
Hamacher et al, "Computer Organization", McGraw-Hill, 1984, pp. 307-313.
Smith, "Cache Memory Design: An Evolving Art", IEEE Spectrum, Dec. 1987, pp. 40-44.
IBM Tech. Disc. Bulletin, "Page Allocation Control", pp. 334-337, Jan. 1990.
IBM Tech. Discl. Bulletin, "Cache Miss History Table", pp. 5978-5980, Apr. 1983.
Digital Equipment Corporation
Donaghue L.
Fisher Arthur W.
Ramirez Ellis B.
Ross Gary E.
LandOfFree
Method and apparatus for cache miss reduction by simulating cach does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for cache miss reduction by simulating cach, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for cache miss reduction by simulating cach will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2187708