Method and apparatus for bus executed boundary scanning

Details Method and apparatus for bus executed boundary scanning Method and apparatus for bus executed boundary scanning

1989-10-19

1992-05-19

Ruggiero, Joseph

Excavating

371 251, 371 221, H04B 1700

Patent

active

051154358

ABSTRACT:
A boundary scan test circuit for inclusion into ASIC and or VLSI circuits which does not require any additional pads/pins to support full boundary scan functionality. The invention uses the power and capability of existing address and data buses to transfer test data into the integrated circuit under boundary scan test, and uses the same buses to transfer test results out of the integrated circuit under test to be interpreted by the test processor of the system.

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IEEE, Feb. 1990, "Designing and Implementing an Architecture with Boundary Scan" by R. P. Van Riessen, et al.
IEEE, Feb. 1989, pp. 36-44, "Boundary Scan with Built-In Self-Test" by Clay S. Gloster, et al.
TI Technical Journal, Jul.-Aug. 1988, pp. 48-59, "A Standard Test Bus and Boundary Scan Archi." by Lee Whetsel.

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