Method and apparatus for bus arbitration in a multiple bus infor

Details Method and apparatus for bus arbitration in a multiple bus infor Method and apparatus for bus arbitration in a multiple bus infor

1994-08-08

1997-01-28

Harvey, Jack B.

395729, 395865, G06F 13372

Patent

active

055985424

ABSTRACT:
In a computer system having a central processing unit (CPU) in circuit communication with a memory via a memory bus and having first and second peripheral bus controllers generating first and second dissimilar peripheral buses, a multibus arbiter is provided for arbitrating access of a memory bus between the two dissimilar buses. The multibus arbiter has an assignment register, a time slot pointer, and an arbitration circuit. The length of the assignment register and time slot pointer controls the granularity of control of accesses to the memory bus by the peripheral buses. The assignment register holds a multibit assignment value that determines which of the two peripheral buses will be given access to the memory bus for a given time slot during contention. The time slot pointer selects one of the bits of the assignment register and points to a different bit responsive to both peripheral buses requesting access to the memory bus at the same time and one of said peripheral bus arbiters indicating that the current access of the memory bus is complete.

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