Method and apparatus for burn-in optimization

Details Method and apparatus for burn-in optimization Method and apparatus for burn-in optimization

2006-10-05

2009-06-16

Nguyen, Ha Tran T (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07548080

ABSTRACT:
The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

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Oleg Semenov et al., “Burn-in Temperature Projections for Deep Sub-micron Technologies”, 2003, IEEE, ITC International Test Conference, Paper 4.3, pp. 95-104.

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