Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-12-04
2002-02-12
Vincent, David R. (Department: 2732)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C710S100000, C710S052000, C711S173000
Reexamination Certificate
active
06347097
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to receiving data from a serial bus and, more particularly, to a method for storing the data in a FIFO and retrieving the data therefrom in an IEEE 1394 serial bus system.
BACKGROUND OF THE INVENTION
The IEEE has proposed a new standard under IEEE 1394 for a high-performance serial bus cable environment that includes a network of logical nodes connected by point-to-point links called physical connections. The physical connections consist of a port on each of the nodes and a cable disposed therebetween. A node can have multiple ports, which allows a branching multi-hop interconnect. The limitations on this topology are set by the requirement for the fixed round-trip time required for the arbitration protocol. The default timing set after a bus reset is adequate for
16
cable hops, each of 4.5 meters for a total of 72 meters. The maximum number of nodes supported on a single bus is 63.
Whenever a node is added to or removed from the 1394 serial bus, a bus reset occurs and forces all nodes to a known state. After a bus reset, the tree identify (ID) process translates the general network topology into a tree, where one node is designated a root, and all the physical connections are labeled as either a parent, a child or as unconnected. The unconnected ports are labeled as “off” and do not participate any further. The tree must be acyclic, meaning no loops allowed; otherwise, the tree ID process will not be completed.
The 1394 cable environment supports multiple data rates of 98.304, 196.608, 393.216 megabits per second. The lowest speed is known as the base rate, and all ports that support a higher data rate must also support the lower data rate. Nodes capable of data rates greater than the base rate exchange speed information with its peers through its attach ports during the speed signaling phase of normal bus arbitration. If a peer node is incapable of receiving high-speed data, then data will not propagate down that path. Data will only be propagated down paths that support the higher data rate.
During data packet transmission, the source node sends a speed code, format and transaction codes, addresses of the source and destination nodes and data in a packet form. The destination field in this packet is utilized by each node's link layer to determine if it is the recipient of the transmitted data. The maximum speed at which a data packet can be transmitted depends upon the bus topology and the data transmission speed supported by the nodes on the bus. To determine the optimum speed at which a data packet may be sent, the maximum supported speeds of the transmitting and receiving nodes, as well as the maximum speeds of any nodes connected between these nodes, must be determined. The optimum speed for data transmission is equal to the highest speed which is supported by all the nodes, which are required to participate in the transmission of the data packet.
The IEEE 1394 bus operates within a 32-bit environment. Data is transmitted in “quadlets,” which are comprised of four bytes of data. At the receive end, these 32-bit quadlets are received and transferred to the host system bus. However, there is an interchange that takes place between the receiving layer and the transmitting layer which requires the receiving layer to receive the various data quadlets and buffer them before receiving the next data quadlets. Additionally, after all the data quadlets in a given packet are received, there is performed an error check on the data which is facilitated by including in the packet a CRC quadlet. If the data is in error, then an acknowledgment signal is sent back to the transmitting layer to indicate that the data was not received correctly. However, since this data is not totally buffered, this can present a problem with having to receive all of the quadlets prior to performing the error checking. To facilitate this data receiving operation, a FIFO (first in, first out) buffer has been utilized for storing the data. To store the data as discrete packets in a FIFO, it is necessary to associate a controlled data bit with each quadlet, this controlled bit therefore increasing the width of the FIFO to 33 bits. Since it is 33 bits, the host system must perform two reads for each quadlet retrieved from the FIFO. Typically, a “1” control data bit indicates the beginning of a data packet, and the end of a data packet with the weight “0” indicating intermediate data quadlets. The last registered position in the FIFO for a given data packet essentially constitutes the acknowledge signal that is sent back to the transmitting node.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises a method and apparatus for buffering received packetized data from a serial bus. The initiation of receipt of a given packet of data is first recognized, and then storage thereof initiated by storing the received data from the packet in a first packet data storage location in a FIFO. Subsequent received data is then stored in additional packet data storage locations in the FIFO as they are received. The end of a given packet data is then recognized and, after this event, a packet token is generated. The packet token contains information as to the packet data storage locations within the FIFO associated with the packet data. This packet data token is stored in the FIFO in such a manner that, upon reading a packet of data by a host system from the FIFO, the packet token will be read first to provide information to the host system as to the packet data storage locations of the remaining data in the stored packet.
In another aspect of the present invention, the packet data storage locations are sequential in nature and adjacent to each other such that a read operation need only increment a Read pointer in the FIFO from one location to the next. The packet data storage location has a width that is equal to the width of the data bus in the host system such that a single read is required to read the contents of the packet data storage location. For each packet data storage location, there is associated therewith a control field that defines the relative location of a packet data storage location within the received packet. The packet token is stored in a packet data storage location that precedes the first packet data storage location for the received packet. The control field associated with the packet token indicates that it is the first packet data storage location associated with the given packet. The host system reads the packet token with two read operations, a first read operation for the packet data storage location and a second read operation for the control field. Once the number of packet locations associated with the packet to be read is determined, only a single read is required for each subsequent data location until a number of packet data storage locations equal to the number indicated by the packet token is read.
REFERENCES:
patent: 5845152 (1998-12-01), Anderson et al.
patent: 5996032 (1999-11-01), Baker
patent: 6006286 (1999-12-01), Baker et al.
patent: 6081852 (2000-06-01), Baker
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Vincent David R.
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