Computer graphics processing and selective visual display system – Display driving control circuitry – Physically integral with display elements
Patent
1996-04-29
1999-06-22
Brier, Jeffery
Computer graphics processing and selective visual display system
Display driving control circuitry
Physically integral with display elements
345507, 345508, H04N 712
Patent
active
059147113
ABSTRACT:
Triple-buffering video memory in a computer graphics controller improves the quality of full-motion video converted for display on a computer monitor. Buffer size, organization, and access cycles prevent converted data representing a new video frame from overwriting a buffer in memory that contains converted data representing a video frame currently being displayed. The access cycles also ensure all data representing a video frame is displayed. The video memory is partitioned into three logical buffers to hold the converted data, the buffers are arranged in a logical ring sequence for read and write access, and the data in a buffer is repeatedly read until the next buffer in the sequence is full of data and ready to be read. In addition, the buffering is adaptable to different resolutions as the size of the buffers is determined by the value of the resolution each time the video conversion is initiated.
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Farwell Randall S.
Mangerson Mark M.
Brier Jeffery
Claiborne Anthony
Gateway 2000 Inc.
Kovalick Vincent E.
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