Method and apparatus for buffering data within stations of a com

Details Method and apparatus for buffering data within stations of a com Method and apparatus for buffering data within stations of a com

1991-04-30

1994-05-17

Shaw, Dale M.

G06F 1202

Patent

active

053135822

ABSTRACT:
Method and apparatus are disclosed for buffering data packets in a data communication controller. The communication controller is interfaced with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a packet number. Packet number assignment is carried out by a memory management unit within the communication controller which dynamically allocates to each assigned packet number one or more pages in a data packet buffer memory for the storage of the corresponding data packet. Upon issuing the assigned packet number, the physical addresses of the allocated pages of data packet buffer memory storage space are generated in a manner transparent to both the host processor and the control unit. Upon completion of each data packet loading operation, the corresponding packet number is stored in a packet number queue maintained for subsequent retrieval in order to generate the physical addresses at which the corresponding data packet has been stored. Also disclosed is a mechanism for automatically generating transmit interrupts to the host processor upon the completion of any preselected number of data packet transmissions determined by the host processor.

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Specification pamphlet of the Intel 82596DX and 82596SX High-Performance 32-Bit Local Area Network Coprocessor, by Intel Corporation, dated Dec., 1988.

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