Method and apparatus for biasing cache LRU for prefetched instru

Details Method and apparatus for biasing cache LRU for prefetched instru Method and apparatus for biasing cache LRU for prefetched instru

1995-04-21

1998-06-30

Lall, Parshotam S.

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395382, 395383, 395582, 395584, 395460, 395461, 395462, 395463, 39580023, 364DIG1, 711122, 711123, 711133, 711137, G06F 938, G06F 1208

Patent

active

057746850

ABSTRACT:
The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations associated with the conditional branches between the time the prefetch request is initiated and the time the prefetched data is actually needed. As a result of this explicit communication of compile-time speculations to the run-time hardware, prefetched lines based on invalid speculations can be discarded earlier, whereas, prefetched lines based on valid speculations can be retained longer in the cache, leading to better cache performance.

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