Method and apparatus for biasing a differential cascode circuit

Details Method and apparatus for biasing a differential cascode circuit Method and apparatus for biasing a differential cascode circuit

1996-10-25

1998-05-19

Mottola, Steven

Amplifiers

With semiconductor amplifying device

Including plural stages cascaded

330261, H03F 345

Patent

active

057540799

ABSTRACT:
A method and apparatus for biasing a differential cascade circuit are provided. The differential cascode circuit includes a first cascade circuit having a first transistor coupled to a second transistor at a first node, and a second cascade circuit having a third transistor coupled to a fourth transistor at a second node. A sensing circuit senses a first differential voltage between the first and second nodes. In response to the sensing of the first differential voltage, a voltage adjusting circuit coupled to the sensing circuit applies a second differential voltage between the gate terminals of the second and fourth transistors such that the first differential voltage is minimized.

REFERENCES:
patent: 4366446 (1982-12-01), Henderson et al.
patent: 5202645 (1993-04-01), Phan et al.
patent: 5389891 (1995-02-01), Phillippe
patent: 5444414 (1995-08-01), Delano

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