Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
1998-09-22
2001-06-12
Lee, John R. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S308000
Reexamination Certificate
active
06246043
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to CMOS active pixel sensors. More particularly, the present invention relates to biasing a CMOS active pixel sensor at voltages that exceed the nominal voltage maximums of the CMOS active pixel sensor to maximize the dynamic range in the CMOS active pixel sensor. Further, the present invention relates to biasing to reduce read disturb resulting from impact ionization current phenomenon in the CMOS active pixel sensor.
2. The Related Art
It can be readily observed by those of ordinary skill in the art that the size of the components and interconnect between components in integrated circuits have steadily decreased to permit a greater number of circuits to be formed on a single piece of silicon. As the process technologies shrink the size of the components and interconnect in an integrated circuit, a corresponding decrease in the nominal operating voltages of the components in integrated circuits have also decreased. Unfortunately, the shrinking of the process technology and the corresponding nominal operating voltages of the components in the integrated circuit are not directly scalable in some integrated circuit applications in the sense that the integrated circuit will not operate as desired for the nominal voltages that are typically indicated for the process technology by which the integrated circuit is implemented.
For example, a known CMOS active pixel sensor
10
is depicted in FIG.
1
. The active pixel sensor
10
is fabricated according to a 0.5 um process which provides for a nominal operating voltage of 5.0 volts. In active pixel sensor
10
, a photodiode
12
has an anode connected to ground and a cathode connected to the source of N-Channel MOS reset transistor
14
. The drain of N-Channel MOS reset transistor
14
is connected to a Vref of greater than 3.5 volts and the gate of N-Channel MOS reset transistor
14
is connected to a RESET line.
The cathode of photodiode
12
is also connected to a first source/drain of N-channel MOS transfer transistor
16
. A second source/drain of N-Channel MOS transfer transistor
16
is connected to a first terminal of a storage element
18
and also to the gate of N-channel MOS readout transistor
20
. A second terminal of the storage element
18
is connected to a reference potential shown as ground. The gate of N-Channel MOS transfer transistor
16
is connected to a TRANSFER line. The connection of the second source/drain of N-Channel MOS transfer transistor
16
to the first terminal of storage element
18
and also to the gate of N-Channel MOS transistor
20
forms a storage node
22
.
The drain of N-channel MOS readout transistor
20
is connected to Vcc at greater than about 3.5 volts, and the source of N-channel MOS readout transistor
20
is connected to the drain of N-channel MOS row select transistor
24
. The gate of N-channel MOS row select transistor
20
is connected to a ROW SELECT line, and the source of N-channel MOS row select transistor
24
is connected to a column output line. The drain of an N-channel MOS column bias transistor
26
is connected to the column output line, and the source of N-channel MOS column bias transistor
26
is connected to reference potential shown as ground. The gate of N-channel MOS column bias transistor
26
is connected to a COLUMN BIAS line.
FIG. 2
illustrates a timing diagram of the RESET, TRANSFER, and ROW SELECT signals depicted in
FIG. 2
to aid in explaining the operation of the active pixel sensor
10
. The RESET signal first makes a transition from LOW to HIGH as depicted by reference numeral
30
to turn on the N-channel MOS reset transistor
14
and thereby set the cathode of photodiode
12
to voltage Vref. The N-channel MOS transfer transistor
16
is then turned on when the TRANSFER signal makes a transition from LOW to HIGH as depicted by reference numeral
32
. When the N-channel MOS reset transistor
14
is turned off as RESET signal makes a transition from HIGH to LOW as depicted at reference numeral
34
, integration of photocurrent on photodiode
12
can begin.
While N-channel MOS transfer transistor
16
is turned on, the capacitance of the storage element
18
adds to the capacitance of the photodiode
12
during integration, thereby increasing the charge capacity and the range of the active pixel sensor
10
. This also reduces variation in the pixel output due to capacitance fluctuations since gate oxide capacitance from which storage element
18
is formed is better controlled than junction capacitance of the photodiode
12
. It should be appreciated by those of ordinary skill in the art that as photocharge is captured by the photodiode
12
, the voltage level at storage node
22
decreases from the initial value of Vref at which it was set.
When the photocurrent integration period determined by external exposure control is complete, the N-channel MOS transfer transistor
16
turns off when the TRANSFER signal makes a transition from HIGH to LOW as indicated by reference numeral
36
. The integration period is indicated by reference numeral
38
. Turning off N-channel MOS transfer transistor
16
isolates the voltage level corresponding to the integrated photocharge onto the storage node
22
. It is preferable to reset the photodiode
12
to Vref after the N-channel MOS transfer transistor
16
has been turned off by again turning on N-channel MOS reset transistor
14
as indicated by the RESET signal at reference numeral
40
. This action will prevent the photodiode
12
from continuing to integrate during the read out process and possibly overflowing excess charge into the substrate which could affect the integrity of the signal on the storage node
22
.
Immediately after the N-channel MOS transfer transistor
16
is turned off, the read out process can begin. Each of the active pixel sensors in a row is read when a ROW SELECT signal pulse depicted at reference numeral
42
is applied to the gate of the N-channel MOS row select transistor
24
. In the readout operation of active pixel sensor
10
, when N-channel row select transistor
24
is turned on, a voltage related to the voltage found on storage node
22
is placed on the column output line by N-Channel MOS readout transistor
22
acting as a source follower. The TRANSFER signal stays low until all of the rows have been read out or another cycle is initiated. When the readout operation begins, a HIGH signal applied to the COLUMN BIAS line grounds the column line.
To ensure adequate dynamic range in the image being captured by the active pixel sensor
10
, the Vref must be a high enough voltage level so that when the cathode of the photodiode
12
is set to Vref, the voltage on the cathode of the photodiode
12
can accommodate the captured photocharge for the entire dynamic range of the image being sensed. When the voltage level Vref is not high enough, the brightest levels in the dynamic range corresponding to the highest levels of captured photocharge will not be properly sensed.
From the above discussion, it should be appreciated that the N-channel MOS reset transistor
14
places the voltage Vref at the cathode of the photodiode during a reset period, and the N-channel MOS transfer transistor
16
transfers photocharge captured by the photodiode
12
to the storage node
22
during an integration period, and then isolates the storage node
22
from further collection of photocharge by the cathode of photodiode
12
when the integration period has ended. During reset, the RESET line is preferably driven by a reset signal to a voltage at least a threshold above Vref to set the cathode of the photodiode
12
to Vref, and during the integration period, the TRANSFER line is preferably driven to a voltage that is at least one threshold above the voltage to which the cathode of photodiode
12
has been set at the beginning of the integration period.
It is presently understood by those of ordinary skill in the art that a nominal voltage level of 2.5 volts must be placed at the cathode of the photodiode
12
to ad
Foveon, Inc.
Lee John R.
Sierra Patent Group Ltd.
LandOfFree
Method and apparatus for biasing a CMOS active pixel sensor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for biasing a CMOS active pixel sensor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for biasing a CMOS active pixel sensor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2437850