Etching a substrate: processes – Forming or treating material useful in a capacitor
Reexamination Certificate
1999-09-01
2002-04-09
Gulakowski, Randy (Department: 1746)
Etching a substrate: processes
Forming or treating material useful in a capacitor
C438S462000
Reexamination Certificate
active
06368514
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the manufacture of capacitors. More particularly, the invention relates to the manufacture of thin film discrete capacitors in batch process form.
BACKGROUND OF THE INVENTION
A capacitor is a two terminal passive device comprised of conductors separated by one or more dielectric materials, for storage of charge when a potential difference exists between adjacent conductors. The capacitance C of a capacitor is equal to Q/V, where Q is the charge stored by the capacitor and V is the voltage between the conductors.
Various techniques and materials used in manufacturing capacitors are selected to provide the desired capacitance values and other parameters associated with a capacitor, such as the maximum voltage rating, a power rating, stability with time and temperature and/or an upper and lower temperature tolerance. The capacitance C of a capacitor is dependent on the material and dimensions of the capacitor structure, namely C=&mgr;A/d, where &mgr; is the dielectric constant of the material used for the dielectric between the conductive capacitor plates, A is the overlapping area of adjacent capacitor plates and d is the separation of the overlapping plates. To increase the capacitance of a capacitor, one must increase the capacitor plate area, decrease the separation between capacitor plates and/or use a dielectric with a higher dielectric constant. Accordingly, capacitors connected in parallel increase the amount of total capacitance, while capacitors coupled in series decrease the total capacitance across the series combination.
U.S. Pat. No. 4,017,885 to Kendall et al discloses a semiconductor or integrated circuit capacitor which utilizes grooves in the substrate to increase the capacitance of the capacitor. Other patents disclose various other methods of increasing the capacitance of integrated circuit capacitors used in memory devices such as dynamic random access memories (DRAM). For example, U.S. Pat. No. 5,716,884 discloses a fin-shaped electrode for a DRAM memory cell, increasing capacitance by forming multiple layers of a stacked capacitor. U.S. Pat. No. 5,728, 618 discloses a high capacitance stacked capacitor using one optical mask for two masking steps. U.S. Pat. No. 5,691,223 discloses forming capacitors over bit lines of memory arrays in an integrated circuit. Other patents disclose methods of providing capacitors in the same semiconductor fabrication process as transistors or digital logic elements for processing analog signals or digital signals. For example, U.S. Pat. No. 5,701,025 discloses a semiconductor integrated circuit that would include a resistor and a capacitor together with an insulated gate transistor on a single semiconductor substrate. The general focus of these and other prior art integrated circuit capacitors is that the capacitors are to be manufactured as part of an integrated circuit device that includes other circuitry such as memory and transistors. They are not focused on resolving problems, increasing capacity or improving manufacturing processes for discrete capacitor components.
Methods of increasing capacitance for discrete capacitors, as opposed to integrated circuit capacitors, have involved stacking capacitors together in parallel or using multiple layers of dielectrics and capacitor plates or laminates. Examples of stacking capacitors together in parallel are described in U.S. Pat. Nos. 5,414,588 and 5,486,277. Examples of using multiple layers are described in U.S. Pat. Nos. 5,335,139; 5,600,533; 5,335,139; 5,853,515; 5,736,448; 4,853,827; and 4,4470,099 which disclose methods of manufacturing a single discrete capacitive device. However, these prior art patents do not disclose how to manufacture capacitors in a batch process where multiple discrete capacitors are manufactured simultaneously.
U.S. Pat. Nos. 4,531,268; 4,563,724; 5,663,089 and 5,459,635 disclose manufacturing multiple discrete capacitors nearly simultaneously. U.S. Pat. No. 4,531,268 discloses manufacturing multiple capacitors by a mechanical means by using first and second webs, each having a dielectric substrate, a metallic film coating and narrow parallel longitudinal metal-free zones. U.S. Pat. No. 4,563,724 discloses mother capacitors that are manufactured using mechanical means of tape layers wound onto a drum. Incisions are produced in the mother capacitors so that individual stacks may be subsequently separated from the mother capacitors. While these methods of manufacturing may be satisfactory for certain thicknesses of film capacitors such as thick film, mechanical methods are not the most desirable means for the manufacturing of thin film capacitors. U.S. Pat. No. 5,459,635 and U.S. Pat. No. 5,663,089, related patents, disclose a laminated thin film capacitor having a substrate wherein the metal electrode layers and the dielectric layers are laminated alternately on the substrate, cut to a predetermined size, and then external electrodes are formed by vacuum deposition, sputtering, plating, or coating-baking to obtain a laminated thin film capacitor. While U.S. Pat. No. 5,459,635 and U.S. Pat. No. 5,663,089 disclose using semiconductor manufacturing techniques to manufacture multiple capacitors, their method of forming capacitor terminal electrodes is less than desirable. The terminal electrode formation is not processed in a batch form as are the manufacture of capacitor plates and dielectric layers.
BRIEF SUMMARY OF THE INVENTION
Briefly, the present invention includes a method, apparatus and system for batch processed capacitors using masking techniques as described in the claims. The masking techniques may be a shadow mask (stencil process) or a photo-lithographic process. Capacitors are manufactured in rows by alternately depositing multiple dielectric layers and multiple conductive layers to form capacitor plates at different layers of the structure. The capacitor plates are staggered from one plate layer to the next plate layer such that pairs of capacitor plates in each row are initially integral, alternate rows being joined at different locations. An initial dielectric layer may be deposited, if desired, on a substrate such as ceramic or silicon. Alternatively the layers may be deposited onto a quick release base such as a Teflon belt. The capacitor plates are then sawed at column saw areas to saw through alternate, initially integral plates at each kerf to provide openings to form the capacitor terminals in the resultant kerfs. Alternatively the capacitors may be laser scribed to separate the capacitor plates of the series of capacitors. A light dielectric etch may be used to further expose he end contact regions of the conductive plates, or a backsputtering may be used to clean the contact regions. Side-wall electrodes are then deposited as one conductive layer to make intimate contact with the conductive plates. The conductor layer is then vertically etched to form individual terminals for each capacitor. The capacitors are then sawn along scribe areas to separate the capacitor structures into individual discreet thin film capacitors. The discrete thin film capacitors may be encapsulated if desired for packaging, or shipped without encapsulation for use on surface mount printed circuit boards. Prior to column separation, additional capacitance may be obtained for a thin film discrete capacitor, without decreasing manufacturing throughput, by stacking multiple capacitor structures together in parallel and then performing column separation of the stacked structures. Further processing of the stacked structures in the formation of capacitor terminals is similar to the processing for forming capacitor terminals on a single unit. Advantages to the present invention will be obvious after reading the disclosure. Various embodiments are disclosed
REFERENCES:
patent: 1298396 (1919-03-01), Pruessman
patent: 2841508 (1958-07-01), Roup et al.
patent: 3173974 (1965-03-01), Mohr
patent: 3325699 (1967-06-01), Hellicar
patent: 3520054 (1970-07-01), Pensack et al.
patent: 3582729 (1971-06
Blakely , Sokoloff, Taylor & Zafman LLP
Gulakowski Randy
Luminous Intent, Inc.
Smetana Jiri
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