Pulse or digital communications – Systems using alternating or pulsating current
Patent
1993-01-13
1995-09-26
Chin, Stephen
Pulse or digital communications
Systems using alternating or pulsating current
375240, 375292, 341 54, 341 58, 341177, H04L 2700
Patent
active
054540062
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method of limiting the bandwidth of a selected binary signal, by generating a digital signal which exhibits a continuous series of changes in signal level. The two logic states are each represented by a respective pulse train, which have the respective frequencies f1 and f2.
BACKGROUND ART
Several different digital signal transmission methods are described in the literature. For example, various textbooks describe methods which are generally known under the designations NRZ-coding, Bifas-coding and DM-coding. See, for instance, the product catalogue "Z16C30 CMOS USC Universal Serial Controller", May 1989, ZILOG Inc., Campbell, Calif. 95008-6609, U.S.A., page 8.
The most simplest and the most common coding method is the NRZ method (Non Return to Zero), which implies that a logic one is represented by a high signal and a logic zero is represented by a low signal (or vice versa). NRZ-signalling requires a transmission channel that has a bandwidth of from 0 to 1/TB Hz, where TB is the duration of a data bit in seconds. The NRZ-code has a large direct voltage (DC) component, which renders it unsuitable when the lower band limit differs from 0. Neither does NRZ coding ensure that a minimum time lapse between two mutually sequential changes in signal level will always be present in any given binary data signal, which means that a clock signal representing the position of each data signal bit, cannot be obtained from the data signal, but must be transmitted on a separate channel.
Another method is the Bi-phase code method. In the Bi-phase code, at least one and at most two changes in signal level always occur with each bit interval. Although this enables the clock signal to be obtained from the coded signal, the bandwidth of the transmission channel is increased to 0-2/TB. The most serious drawback with the Bi-phase codes is that the upper band limit is twice the upper band limit with NRZ signalling.
The Manchester code is a variant of Bi-phase modulation, also known as Biphase-level, where a logic one is coded as 1/2TB high signal level followed by 1/2TB low signal level and a logic zero is coded as 1/2TB low signal level followed by 1/2TB high signal level. The Manchester code is therefore dependent on polarity.
The DM-code (Delay Modulation) or the Miller code is another method which, similar to the Bi-phase code, enables the clock signal to be regenerated from the modulated data signal, but lacks the drawback of the Bi-phase code with respect to the high upper band limit. The DM-code modulated data signal, however, is completely void of direct voltage components. In DM, a logic one is coded as a change in signal level in the middle of the bit interval and a logic zero is coded as a change in signal level at the end of the bit interval, only if it is followed by a further zero.
Both the Manchester codes and the DM codes also have the drawback that in the case of an infinite stream of ones or zeroes, the modulated data signal is identical to the phase shift of solely 1/2 data bit. This results in a synchronization problem, since it is necessary for the receiver (the decoder) to be aware of the phase position in order to be able to decode the modulated signal correctly.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method which will avoid the drawbacks associated with the known methods and to modulate a digital signal so that the resultant signal will be more suited for transmission over bandwidth limited media, for example a cable.
This is achieved in accordance with the invention in that the frequencies f1, f2 of the pulse train of the modulated digital signal are mutually different, and in that the higher frequency, f2, is equal to the number of data bits per second divided by two (1/2TB). The transition between the two pulse positions is arranged so that the integral or Run Length Digital Sum (RDS) of the resultant signal will be equal to zero within the duration of four transmitted data bits (4TB).
The modulated signal i
REFERENCES:
patent: 4101934 (1978-07-01), Fukuoka
patent: 4153814 (1979-05-01), Burgert
patent: 4369472 (1983-01-01), Tanaka et al.
patent: 4626826 (1986-12-01), Fukuda et al.
patent: 4747113 (1988-05-01), Viallevicille
Chin Stephen
Unitex AB
Vo Don
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