Patent
1993-07-28
1996-01-02
Beausoliel, Jr., Robert W.
G11C 2900
Patent
active
054816700
ABSTRACT:
A multi-memory apparatus, configured only with identical memory units with access to the common system bus, provides secure data identity in the event of various errors by using synchronous as well as parallel operation. A memory unit in a multi-memory apparatus includes a refresh request circuit, a bus control circuit, a bus-response circuit as well as a control circuit. A master refresh request circuit issues a memory-refresh request by using the bus clock and a backup refresh request circuit issues a memory-refresh request by a trigger from the master memory. A master bus control circuit responds to the system bus and a backup bus control circuit prohibits the unit from responding. A master bus-response control circuit allows the bus control circuit to respond to the system bus and changes mode between memory units from master/backup to backup/master in the event of an error detected in the master memory unit.
REFERENCES:
patent: 4150428 (1979-04-01), Inrig et al.
patent: 4380812 (1983-04-01), Ziegler, II et al.
patent: 4597084 (1986-06-01), Dynneson et al.
patent: 4603406 (1986-07-01), Miyazaki
patent: 4849978 (1989-07-01), Dishon
patent: 5177744 (1993-01-01), Cesare
patent: 5197026 (1993-03-01), Butler
patent: 5325333 (1994-07-01), Sato
Hatashita Toyohito
Shimizu Toshihiko
Taura Motoharu
Umeoka Hiroshi
Beausoliel, Jr. Robert W.
Mitsubishi Denki & Kabushiki Kaisha
Snyder Glenn
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